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1995 microchip technology inc. ds30390b-page 1 pic16c7x 8-bit cmos microcontrollers with a/d converter devices included in this data sheet: PIC16C70 pic16c71 pic16c71a pic16c72 pic16c73 pic16c73a pic16c74 pic16c74a pic16c7x microcontroller core features: high-performance risc cpu only 35 single word instructions to learn all single cycle instructions (200 ns) except for program branches which are two cycle operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle interrupt capability eight level deep hardware stack direct, indirect and relative addressing modes power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code-protection power saving sleep mode selectable oscillator options 8-bit multichannel analog-to-digital converter low-power, high-speed cmos eprom technology fully static design wide operating voltage range: 3.0v to 6.0v high sink/source current 25/25 ma commercial, industrial and automotive tempera- ture range low-power consumption: - < 2 ma @ 5v, 4 mhz - 15 m a typical @ 3v, 32 khz - < 1 m a typical standby current pic16c7x peripheral features: timer0: 8-bit timer/counter with 8-bit prescaler timer1: 16-bit timer/counter. tmr1 can be incre- mented during sleep via external crystal/clock timer2: 8-bit timer/counter with 8-bit period regis- ter, prescaler and postscaler capture, compare, pwm module(s) capture is 16-bit, max. resolution 12.5 ns, com- pare is 16-bit, max. resolution 200 ns, max. pwm resolution is 10-bit synchronous serial port (ssp) with spi ? and i 2 c ? universal synchronous asynchronous receiver transmitter (usart/sci) parallel slave port (psp) 8-bit wide, with external rd , wr and cs controls brown-out detection circuitry for brown-out reset (bor) pic16c7x features 70 71 71a 72 73 73a 74 74a program memory (eprom) 512 1k 1k 2k 4k 4k 4k 4k data memory (bytes) 36 36 68 128 192 192 192 192 i/o pins 13 13 13 22 22 22 33 33 parallel slave port yes yes capture/compare/pwm modules 1 2 2 2 2 timer modules 1 1 1 3 3 3 3 3 a/d channels 4 4 4 5 5 5 8 8 serial communication spi/i 2 c spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart spi/i 2 c, usart in-circuit serial programming yes yes yes yes yes yes yes yes brown-out reset yes yes yes yes yes interrupt sources 4 4 4 8 11 11 12 12 i 2 c is a trademark of philips corporation. spi is a trademark of motorola corporation. this document was created with framemake r404
pic16c7x ds30390b-page 2 1995 microchip technology inc. pin diagrams PIC16C70 ra2/an2 ra3/an3/v ref ra4/t0cki mclr /v pp v ss v ss rb0/int rb1 rb2 rb3 ra1/an1 ra0/an0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ?1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd ssop ra2/an2 ra3/an3/v ref ra4/t0cki mclr /v pp v ss rb0/int rb1 rb2 rb3 ra1/an1 ra0/an0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ?1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 PIC16C70 pdip, soic, windowed cerdip pic16c71a ra2/an2 ra3/an3/v ref ra4/t0cki mclr /v pp v ss v ss rb0/int rb1 rb2 rb3 ra1/an1 ra0/an0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ?1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd ssop ra2/an2 ra3/an3/v ref ra4/t0cki mclr /v pp v ss rb0/int rb1 rb2 rb3 ra1/an1 ra0/an0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ?1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pic16c71a pdip, soic, windowed cerdip ra2/an2 ra3/an3/v ref ra4/t0cki mclr /v pp v ss rb0/int rb1 rb2 rb3 ra1/an1 ra0/an0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ?1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pic16c71 pdip, soic, windowed cerdip pic16c72 mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4/ss v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7 rc6 rc5/sdo rc4/sdi/sda ?1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sdip, soic, windowed side brazed ceramic pic16c72 mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4/ss v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7 rc6 rc5/sdo rc4/sdi/sda ?1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ssop
1995 microchip technology inc. ds30390b-page 3 pic16c7x pin diagrams (cont.d) pic16c73 mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4/ss v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda ?1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pic16c73a sdip, soic, windowed side brazed ceramic nc rc0/t1oso/t1cki osc2/clkout osc1/clkin v ss v dd re2/cs /an7 re1/wr /an6 re0/rd /an5 ra5/an4/ss ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp rb7 rb6 rb5 rb4 nc nc 44 43 42 41 40 39 38 37 36 35 34 22 21 20 19 18 17 16 15 14 13 12 pic16c74 mqfp rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt ra4/t0cki ra5/an4/ss re0/rd /an5 re1/wr /an6 re2/cs /an7 v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki nc ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp nc rb7 rb6 rb5 rb4 nc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 pic16c74 /ccp2 nc rc0/t1oso/t1cki osc2/clkout osc1/clkin v ss v dd re2/cs /an7 re1/wr /an6 re0/rd /an5 ra5/an4/ss ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 mclr /v pp rb7 rb6 rb5 rb4 nc nc 44 43 42 41 40 39 38 37 36 35 34 22 21 20 19 18 17 16 15 14 13 12 pdip, windowed cerdip mqfp plcc rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4/ss re0/rd /an5 re1/wr /an6 re2/cs /an7 v dd v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16c74 pic16c74a pic16c74a pic16c74a tqfp
pic16c7x ds30390b-page 4 1995 microchip technology inc. table of contents 1.0 general description ................................................................................................................................................5 2.0 pic16c7x device varieties ....................................................................................................................................7 3.0 architectural overview............................................................................................................................................9 4.0 memory organization ...........................................................................................................................................21 5.0 i/o ports ...............................................................................................................................................................43 6.0 overview of timer modules ..................................................................................................................................57 7.0 timer0 module......................................................................................................................................................59 8.0 timer1 module......................................................................................................................................................65 9.0 timer2 module......................................................................................................................................................69 10.0 capture/compare/pwm module(s) ......................................................................................................................71 11.0 synchronous serial port (ssp) module ...............................................................................................................77 12.0 universal synchronous asynchronous receiver transmitter (usart) ...............................................................93 13.0 analog-to-digital converter (a/d) module ..........................................................................................................109 14.0 special features of the cpu ..............................................................................................................................121 15.0 instruction set summary ....................................................................................................................................141 16.0 development support .........................................................................................................................................153 17.0 electrical characteristics for PIC16C70 and pic16c71a ..................................................................................159 18.0 dc and ac characteristics graphs and tables for PIC16C70 and pic16c71a ................................................173 19.0 electrical characteristics for pic16c71 .............................................................................................................175 20.0 dc and ac characteristics graphs and tables for pic16c71 ...........................................................................189 21.0 electrical characteristics for pic16c72 .............................................................................................................197 22.0 dc and ac characteristics graphs and tables for pic16c72 ...........................................................................217 23.0 electrical characteristics for pic16c73/74 ........................................................................................................219 24.0 dc and ac characteristics graphs and tables for pic16c73/74 ......................................................................241 25.0 electrical characteristics for pic16c73a/74a....................................................................................................243 26.0 dc and ac characteristics graphs and tables for pic16c73a/74a .................................................................265 27.0 packaging information ........................................................................................................................................267 appendix a: .................................................................................................................................................................283 appendix b: compatibility ...........................................................................................................................................283 appendix c: whats new.............................................................................................................................................284 appendix d: whats changed .....................................................................................................................................284 appendix e: pic16/17 microcontrollers.......................................................................................................................285 index ...................................................................................................................................................................293 connecting to microchip bbs .............................................................................................................................303 reader response...............................................................................................................................................304 product information system ...............................................................................................................................305 for register and module descriptions in this data sheet, device legends show which devices apply to those sections. as an example, the legend below would mean that the following section applies only to the pic16c71a, pic16c72, pic16c73a and pic16c74a devices. applicable devices 70 71 71a 72 73 73a 74 74a to our valued customers we constantly strive to improve the quality of all our products and documentation. we have spent an exceptional amount of time to ensure that these documents are correct. however, we realize that we may have missed a few things. if you ?d any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. we appreciate your assistance in making this a better document.
1995 microchip technology inc. ds30390b-page 5 pic16c7x 1.0 general description the pic16c7x is a family of low-cost, high-perfor- mance, cmos, fully-static, 8-bit microcontrollers with integrated analog-to-digital (a/d) converters, in the pic16cxx mid-range family. all pic16/17 microcontrollers employ an advanced risc architecture. the pic16cxx microcontroller fam- ily has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. the separate instruction and data buses of the harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. the two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). a total of 35 instructions (reduced instruction set) are available. additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. pic16cxx microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. the PIC16C70/71 devices have 36 bytes of ram, and the pic16c71a has 68 bytes of ram. the PIC16C70/71/71a devices have 13 i/o pins. in addition a timer/counter is available. also a 4-channel high- speed 8-bit a/d is provided. the 8-bit resolution is ide- ally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc. the pic16c72 device has 128 bytes of ram and 22 i/o pins. in addition several peripheral features are available including: three timer/counters, one cap- ture/compare/pwm module and one serial port. the synchronous serial port can be con?ured as either a 3-wire serial peripheral interface (spi) or the two-wire inter-integrated circuit (i 2 c) bus. also a 5-channel high-speed 8-bit a/d is provided. the 8-bit resolution is ideally suited for applications requiring low-cost ana- log interface, e.g. thermostat control, pressure sens- ing, etc. the pic16c73/73a devices have 192 bytes of ram and 22 i/o pins. in addition, several peripheral features are available including: three timer/counters, two cap- ture/compare/pwm modules and two serial ports. the synchronous serial port can be con?ured as either a 3-wire serial peripheral interface (spi) or the two-wire inter-integrated circuit (i 2 c) bus. the universal syn- chronous asynchronous receiver transmitter (usart) is also known as the serial communications interface or sci. also a 5-channel high-speed 8-bit a/d is provided.the 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc. the pic16c74/74a devices have 192 bytes of ram and 33 i/o pins. in addition several peripheral features are available including: three timer/counters, two cap- ture/compare/pwm modules and two serial ports. the synchronous serial port can be con?ured as either a 3-wire serial peripheral interface (spi) or the two-wire inter-integrated circuit (i 2 c) bus. the universal syn- chronous asynchronous receiver transmitter (usart) is also known as the serial communications interface or sci. an 8-bit parallel slave port is pro- vided. also an 8-channel high-speed 8-bit a/d is pro- vided. the 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc. the pic16c7x family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. there are four oscillator options, of which the single pin rc oscillator provides a low-cost solution, the lp oscil- lator minimizes power consumption, xt is a standard crystal, and the hs is for high speed crystals. the sleep (power-down) feature provides a power saving mode. the user can wake up the chip from sleep through several external and internal interrupts and reset(s). a highly reliable watchdog timer with its own on-chip rc oscillator provides protection against software lock- up. a uv erasable cerdip packaged version is ideal for code development while the cost-effective one-time- programmable (otp) version is suitable for production in any volume. the pic16c7x family fits perfectly in applications rang- ing from security and remote sensors to appliance con- trol and automotive. the eprom technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. the small footprint packages make this microcontroller series perfect for all applications with space limitations. low cost, low power, high performance, ease of use and i/o ?xibility make the pic16c7x very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, serial communication, cap- ture and compare, pwm functions and coprocessor applications). 1.1 f amil y and upwar d compatibility users familiar with the pic16c5x microcontroller fam- ily will realize that this is an enhanced version of the pic16c5x architecture. please refer to appendix a for a detailed list of enhancements. code written for the pic16c5x can be easily ported to the pic16cxx fam- ily of devices (appendix b). 1.2 de vel opment suppor t the pic16cxx family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. a ??compiler and fuzzy logic support tools are also available. (section 16.0) this document was created with framemake r404
pic16c7x ds30390b-page 6 1995 microchip technology inc. table 1-1: pic16c7x family of devices PIC16C70 (1) 20 512 36 tmr0 4 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c71 20 1k 36 tmr0 4 4 13 3.0-6.0 yes 18-pin dip, soic pic16c71a (1) 20 1k 68 tmr0 4 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c72 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 5 8 22 3.0-6.0 yes yes 28-pin sdip, soic, ssop pic16c73 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 3.0-6.0 yes 28-pin sdip, soic pic16c73a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 3.0-6.0 yes yes 28-pin sdip, soic pic16c74 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c74a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 3.0-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port a/d converter (8-bit) channels interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features in-circuit serial programming
1995 microchip technology inc. ds30390b-page 7 pic16c7x 2.0 pic16c7x device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in the pic16c7x product selec- tion system section at the end of this data sheet. when placing orders, please use that page of the data sheet to specify the correct part number. for the pic16c7x family, there are two device ?ypes as indicated in the device number: 1. c , as in pic16 c 74. these devices have eprom type memory and operate over the standard voltage range. 2. lc , as in pic16 lc 74. these devices have eprom type memory and operate over an extended voltage range. 2.1 uv erasab le de vices the uv erasable version, offered in cerdip package, is optimal for prototype development and pilot pro- grams. the uv erasable version can be erased and repro- grammed to any of the con?uration modes. microchip's picstart ? and pro mate ? program- mers both support the pic16c7x. third party program- mers also are available; refer to the microchip third party guide for a list of sources. 2.2 one-time-pr ogrammab le (o tp) de vices the availability of otp devices is especially useful for customers who need the ?xibility for frequent code updates and small volume applications. the otp devices, packaged in plastic packages, per- mit the user to program them once. in addition to the program memory, the con?uration bits must also be programmed. 2.3 q uic k-t urnar ound-pr oduction (qtp) de vices microchip offers a qtp programming service for fac- tory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi- lized. the devices are identical to the otp devices but with all eprom locations and con?uration options already programmed by the factory. certain code and prototype veri?ation procedures apply before produc- tion shipments are available. please contact your local microchip technology sales of?e for more details. 2.4 serializ ed quic k-t urnar ound pr oduction (sqtp sm ) de vices microchip offers a unique programming service where a few user-de?ed locations in each device are pro- grammed with different serial numbers. the serial num- bers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number which can serve as an entry-code, password or id number. this document was created with framemake r404
pic16c7x ds30390b-page 8 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30390b-page 9 pic16c7x 3.0 architectural overview the high performance of the pic16cxx family can be attributed to a number of architectural features com- monly found in risc microprocessors. to begin with, the pic16cxx uses a harvard architecture, in which, program and data are accessed from separate memo- ries using separate buses. this improves bandwidth over traditional von neumann architecture where pro- gram and data are fetched from the same memory using the same bus. separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 14-bits wide making it possible to have all single word instructions. a 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. a two- stage pipeline overlaps fetch and execution of instruc- tions (example 3-1). consequently, all instructions (35) execute in a single cycle (200 ns @ 20 mhz) except for program branches. the table below lists program memory (eprom) and data memory (ram) for each pic16c7x device. the pic16cxx can directly or indirectly address its register ?es or data memory. all special function regis- ters, including the program counter, are mapped in the data memory. the pic16cxx has an orthogonal (sym- metrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?pecial optimal situations make programming with the pic16cxx simple yet ef?ient. in addition, the learning curve is reduced signi?antly. device program memory data memory PIC16C70 512 x 14 36 x 8 pic16c71 1k x 14 36 x 8 pic16c71a 1k x 14 68 x 8 pic16c72 2k x 14 128 x 8 pic16c73 4k x 14 192 x 8 pic16c73a 4k x 14 192 x 8 pic16c74 4k x 14 192 x 8 pic16c74a 4k x 14 192 x 8 pic16cxx devices contain an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between the data in the working register and any register ?e. the alu is 8-bits wide and capable of addition, sub- traction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's comple- ment in nature. in two-operand instructions, typically one operand is the working register (w register). the other operand is a ?e register or an immediate con- stant. in single operand instructions, the operand is either the w register or a ?e register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. this document was created with framemake r404
pic16c7x ds30390b-page 10 1995 microchip technology inc. figure 3-1: PIC16C70/71/71a block diagram eprom program memory 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss timer0 a/d porta portb rb0/int rb7:rb1 8 8 brown-out reset (2) note 1: higher order bits are from the status register. 2: brown-out reset is not available on the pic16c71. device program memory data memory (ram) PIC16C70 pic16c71 pic16c71a 512 x 14 1k x 14 1k x 14 36 x 8 36 x 8 68 x 8 ra4/t0cki ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 8 3
1995 microchip technology inc. ds30390b-page 11 pic16c7x figure 3-2: pic16c72 block diagram eprom program memory 2k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 128 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss timer0 a/d synchronous serial port porta portb portc rb0/int rb7:rb1 rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6 rc7 8 8 brown-out reset note 1: higher order bits are from the status register. ccp1 timer1 timer2 ra4/t0cki ra5/an4/ss ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 8 3
pic16c7x ds30390b-page 12 1995 microchip technology inc. figure 3-3: pic16c73/73a block diagram eprom program memory 4k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 192 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss usart porta portb portc rb0/int rb7:rb1 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt 8 8 brown-out reset (2) note 1: higher order bits are from the status register. 2: brown-out reset is not available on the pic16c73. ccp1 ccp2 synchronous a/d timer0 timer1 timer2 serial port ra4/t0cki ra5/an4/ss ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 8 3
1995 microchip technology inc. ds30390b-page 13 pic16c7x figure 3-4: pic16c74/74a block diagram eprom program memory 4k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 192 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc portd porte ra4/t0cki ra5/an4/ss rb0/int rb7:rb1 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt rd7/psp7:rd0/psp0 re0/rd /an5 re1/wr /an6 re2/cs /an7 8 8 brown-out reset (2) note 1: higher order bits are from the status register. 2: brown-out reset is not available on the pic16c74. usart ccp1 ccp2 synchronous a/d timer0 timer1 timer2 serial port ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 parallel slave port 8 3
pic16c7x ds30390b-page 14 1995 microchip technology inc. table 3-1: PIC16C70/71a pinout description pin name dip pin# ssop pin# soic pin# i/o/p type buffer type description osc1/clkin 16 18 16 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 15 17 15 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 4 4 4 i/p st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 17 19 17 i/o ttl analog input0 ra1/an1 18 20 18 i/o ttl analog input1 ra2/an2 1 1 1 i/o ttl analog input2 ra3/an3/v ref 2 2 2 i/o ttl analog input3/v ref ra4/t0cki 3 3 3 i/o st can also be selected to be the clock input to the timer0 module. output is open drain type. portb is a bi-directional i/o port. portb can be software pro- grammed for internal weak pull-up on all inputs. rb0/int 6 7 6 i/o ttl/st (1) rb0/int can also be selected as an external interrupt pin. rb1 7 8 7 i/o ttl rb2 8 9 8 i/o ttl rb3 9 10 9 i/o ttl rb4 10 11 10 i/o ttl interrupt on change pin. rb5 11 12 11 i/o ttl interrupt on change pin. rb6 12 13 12 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 13 14 13 i/o ttl/st (2) interrupt on change pin. serial programming data. v ss 5 4, 6 5 p ground reference for logic and i/o pins. v dd 14 15, 16 14 p positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise.
1995 microchip technology inc. ds30390b-page 15 pic16c7x table 3-2: pic16c71 pinout description pin name dip pin# soic pin# i/o/p type buffer type description osc1/clkin 16 16 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 15 15 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 4 4 i/p st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 17 17 i/o ttl analog input0 ra1/an1 18 18 i/o ttl analog input1 ra2/an2 1 1 i/o ttl analog input2 ra3/an3/v ref 2 2 i/o ttl analog input3/v ref ra4/t0cki 3 3 i/o st can also be selected to be the clock input to the timer0 module. output is open drain type. portb is a bi-directional i/o port. portb can be software pro- grammed for internal weak pull-up on all inputs. rb0/int 6 6 i/o ttl/st (1) rb0/int can also be selected as an external interrupt pin. rb1 7 7 i/o ttl rb2 8 8 i/o ttl rb3 9 9 i/o ttl rb4 10 10 i/o ttl interrupt on change pin. rb5 11 11 i/o ttl interrupt on change pin. rb6 12 12 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 13 13 i/o ttl/st (2) interrupt on change pin. serial programming data. v ss 5 5 p ground reference for logic and i/o pins. v dd 14 14 p positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise.
pic16c7x ds30390b-page 16 1995 microchip technology inc. table 3-3: pic16c72 pinout description pin name dip pin# ssop pin# soic pin# i/o/p type buffer type description osc1/clkin 9 9 9 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 10 10 10 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, the osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 1 1 i/p st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 2 2 2 i/o ttl analog input0 ra1/an1 3 3 3 i/o ttl analog input1 ra2/an2 4 4 4 i/o ttl analog input2 ra3/an3/v ref 5 5 5 i/o ttl analog input3/v ref ra4/t0cki 6 6 6 i/o st can also be selected to be the clock input to the timer0 module. output is open drain type. ra5/an4/ss 7 7 7 i/o ttl analog input4 can also be the slave select for the syn- chronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 21 21 21 i/o ttl/st (1) rb0/int can also be selected as an external interrupt pin. rb1 22 22 22 i/o ttl rb2 23 23 23 i/o ttl rb3 24 24 24 i/o ttl rb4 25 25 25 i/o ttl interrupt on change pin. rb5 26 26 26 i/o ttl interrupt on change pin. rb6 27 27 27 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 28 28 28 i/o ttl/st (2) interrupt on change pin. serial programming data. portc is a bi-directional i/o port. rc0/t1oso/t1cki 11 11 11 i/o st rc0/t1oso/t1cki can also be selected as a timer1 oscillator output/timer1 clock input. rc1/t1osi 12 12 12 i/o st rc1/t1osi/ccp2 can also be selected as a timer1 oscillator input or capture2, input/compare2 output/ pwm2 output. rc2/ccp1 13 13 13 i/o st rc2/ccp1 can also be selected as a capture1 input/ compare1 output/pwm1 output. rc3/sck/scl 14 14 14 i/o st rc3/sck/scl can also be selected as the synchronous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 15 15 15 i/o st rc4/sdi/sda can also be selected as the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 16 16 16 i/o st rc5/sdo can also be selected as the spi data out (spi mode). rc6 17 17 17 i/o st rc7 18 18 18 i/o st v ss 8, 19 8, 19 8, 19 p ground reference for logic and i/o pins. v dd 20 20 20 p positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise.
1995 microchip technology inc. ds30390b-page 17 pic16c7x table 3-4: pic16c73/73a pinout description pin name dip pin# soic pin# i/o/p type buffer type description osc1/clkin 9 9 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 10 10 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, the osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 1 i/p st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 2 2 i/o ttl analog input0 ra1/an1 3 3 i/o ttl analog input1 ra2/an2 4 4 i/o ttl analog input2 ra3/an3/v ref 5 5 i/o ttl analog input3/v ref ra4/t0cki 6 6 i/o st can also be selected to be the clock input to the timer0 module. output is open drain type. ra5/an4/ss 7 7 i/o ttl analog input4 can also be the slave select for the syn- chronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 21 21 i/o ttl/st (1) rb0/int can also be selected as an external interrupt pin. rb1 22 22 i/o ttl rb2 23 23 i/o ttl rb3 24 24 i/o ttl rb4 25 25 i/o ttl interrupt on change pin. rb5 26 26 i/o ttl interrupt on change pin. rb6 27 27 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 28 28 i/o ttl/st (2) interrupt on change pin. serial programming data. portc is a bi-directional i/o port. rc0/t1oso/t1cki 11 11 i/o st rc0/t1oso/t1cki can also be selected as a timer1 oscillator output/timer1 clock input. rc1/t1osi/ccp2 12 12 i/o st rc1/t1osi/ccp2 can also be selected as a timer1 oscillator input or capture2 input/compare2 output/ pwm2 output. rc2/ccp1 13 13 i/o st rc2/ccp1 can also be selected as a capture1 input/ compare1 output/pwm1 output. rc3/sck/scl 14 14 i/o st rc3/sck/scl can also be selected as the synchronous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 15 15 i/o st rc4/sdi/sda can also be selected as the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 16 16 i/o st rc5/sdo can also be selected as the spi data out (spi mode). rc6/tx/ck 17 17 i/o st rc6/tx/ck can also be selected as asynchronous transmit or usart synchronous clock. rc7/rx/dt 18 18 i/o st rc7/rx/dt can also be selected as the asynchronous receive or usart synchronous data. v ss 8, 19 8, 19 p ground reference for logic and i/o pins. v dd 20 20 p positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise.
pic16c7x ds30390b-page 18 1995 microchip technology inc. table 3-5: pic16c74/74a pinout description pin name dip pin# plcc pin# qfp pin# i/o/p type buffer type description osc1/clkin 13 14 30 i st/cmos (4) oscillator crystal input/external clock source input. osc2/clkout 14 15 31 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 2 18 i/p st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 2 3 19 i/o ttl analog input0 ra1/an1 3 4 20 i/o ttl analog input1 ra2/an2 4 5 21 i/o ttl analog input2 ra3/an3/v ref 5 6 22 i/o ttl analog input3/v ref ra4/t0cki 6 7 23 i/o st can also be selected to be the clock input to the timer0 timer/counter. output is open drain type. ra5/an4/ss 7 8 24 i/o ttl analog input4 can also be the slave select for the syn- chronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 33 36 8 i/o ttl/st (1) rb0/int can also be selected as an external interrupt pin. rb1 34 37 9 i/o ttl rb2 35 38 10 i/o ttl rb3 36 39 11 i/o ttl rb4 37 41 14 i/o ttl interrupt on change pin. rb5 38 42 15 i/o ttl interrupt on change pin. rb6 39 43 16 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 40 44 17 i/o ttl/st (2) interrupt on change pin. serial programming data. legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise.
1995 microchip technology inc. ds30390b-page 19 pic16c7x portc is a bi-directional i/o port. rc0/t1oso/t1cki 15 16 32 i/o st rc0/t1oso/t1cki can also be selected as a timer1 oscillator output or a timer1 clock input. rc1/t1osi/ccp2 16 18 35 i/o st rc1/t1osi/ccp2 can also be selected as a timer1 oscillator input or capture2 input/compare2 output/ pwm2 output. rc2/ccp1 17 19 36 i/o st rc2/ccp1 can also be selected as a capture1 input/ compare1 output/pwm1 output. rc3/sck/scl 18 20 37 i/o st rc3/sck/scl can also be selected as the synchro- nous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 23 25 42 i/o st rc4/sdi/sda can also be selected as the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 24 26 43 i/o st rc5/sdo can also be selected as the spi data out (spi mode). rc6/tx/ck 25 27 44 i/o st rc6/tx/ck can also be selected as asynchronous transmit or usart synchronous clock. rc7/rx/dt 26 29 1 i/o st rc7/rx/dt can also be selected as the asynchro- nous receive or usart synchronous data. portd is a bi-directional i/o port or parallel slave port when interfacing to a microprocessor bus. rd0/psp0 19 21 38 i/o st/ttl (3) rd1/psp1 20 22 39 i/o st/ttl (3) rd2/psp2 21 23 40 i/o st/ttl (3) rd3/psp3 22 24 41 i/o st/ttl (3) rd4/psp4 27 30 2 i/o st/ttl (3) rd5/psp5 28 31 3 i/o st/ttl (3) rd6/psp6 29 32 4 i/o st/ttl (3) rd7/psp7 30 33 5 i/o st/ttl (3) porte is a bi-directional i/o port. re0/rd /an5 8 9 25 i/o st/ttl (3) re0/rd /an5 read control for parallel slave port, or analog input5. re1/wr /an6 9 10 26 i/o st/ttl (3) re1/wr /an6 write control for parallel slave port, or analog input6. re2/cs /an7 10 11 27 i/o st/ttl (3) re2/cs /an7 select control for parallel slave port, or analog input7. v ss 12,31 13,34 6,29 p ground reference for logic and i/o pins. v dd 11,32 12,35 7,28 p positive supply for logic and i/o pins. nc 1,17,28, 40 12,13, 33,34 these pins are not internally connected. these pins should be left unconnected. table 3-5: pic16c74/74a pinout description (cont.d) pin name dip pin# plcc pin# qfp pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power ?= not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when con?ured as an external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when con?ured in rc oscillator mode and a cmos input otherwise.
pic16c7x ds30390b-page 20 1995 microchip technology inc. 3.1 cloc king sc heme/ instruction cyc le the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks namely q1, q2, q3 and q4. internally, the pro- gram counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clocks and instruction execution ?w is shown in figure 3-5. 3.2 instruction flo w/pipelining an ?nstruction cycle?consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g. goto ) then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?nstruction register" (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-5: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ushed?from the pipeline while the new instruction is being fetched and then executed. 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 fetch 4 flush fetch sub_1 execute sub_1
1995 microchip technology inc. ds30390b-page 21 pic16c7x 4.0 memory organization 4.1 pr ogram memor y or ganization the pic16c7x family has a 13-bit program counter capable of addressing an 8k x 14 program memory space. for the PIC16C70, only the ?st 512 x 14 (0000h- 01ffh) is physically implemented. for the pic16c71/71a only the ?st 1k x 14 (0000h-03ffh) is implemented. for the pic16c72, only the ?st 2k x 14 (0000h-07ff) is implemented. for the pic16c73, pic16c73a, pic16c74, and pic16c74a, only the ?st 4k x 14 (0000h-0fffh) is physically implemented. accessing a location above the physically implemented address will cause a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 4-1: PIC16C70 program memory map and stack applicable devices 70 71 71a 72 73 73a 74 74a pc<12:0> 13 0000h 0004h 0005h 01ffh 0200h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw figure 4-2: pic16c71/71a program memory map and stack pc<12:0> 13 0000h 0004h 0005h 03ffh 0200h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw this document was created with framemake r404
pic16c7x ds30390b-page 22 1995 microchip technology inc. figure 4-3: pic16c72 program memory map and stack pc<12:0> 13 0000h 0004h 0005h 07ffh 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw 0800h figure 4-4: pic16c73/73a/74/74a program memory map and stack 4.2 d ata memor y or ganization the data memory is partitioned into two banks which contain the general purpose registers and the special function registers. bit rp0 is the bank select bit. rp0 (status<5>) = 1 ? bank 1 rp0 (status<5>) = 0 ? bank 0 each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers implemented as static ram. both bank 0 and bank 1 contain special function registers. some "high use" special function registers from bank 0 are mirrored in bank 1 for code reduction and quicker access. 4.2.1 general purpose register file the register ?e can be accessed either directly, or indi- rectly through the file select register fsr (section 4.5). applicable devices 70 71 71a 72 73 73a 74 74a pc<12:0> 13 0000h 0004h 0005h 07ffh 0800h 0fffh 1000h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program on-chip program memory (page 1) memory (page 0) call, return retfie, retlw
1995 microchip technology inc. ds30390b-page 23 pic16c7x figure 4-5: PIC16C70/71 register file map indf (1) tmr0 pcl status fsr porta portb pclath intcon adres adcon0 indf (1) option pcl status fsr trisa trisb pclath intcon adcon1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch general purpose register 7fh ffh bank 0 bank 1 file address adres 2fh 30h afh b0h unimplemented data memory locations, read as '0'. note 1: not a physical register. 2: the pcon register is not implemented on the pic16c71. 3: these locations are unimplemented in bank 1. any access to these locations will access the corresponding bank 0 register. file address general purpose register mapped in bank 0 (3) pcon (2) figure 4-6: pic16c71a register file map indf (1) tmr0 pcl status fsr porta portb pclath intcon adres adcon0 indf (1) option pcl status fsr trisa trisb pclath intcon adcon1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch general purpose register 7fh ffh bank 0 bank 1 file address adres 4fh 50h cfh d0h unimplemented data memory locations, read as '0'. note 1: not a physical register. 2: these locations are unimplemented in bank 1. any access to these locations will access the corresponding bank 0 register. file address general purpose register mapped in bank 0 (2) pcon
pic16c7x ds30390b-page 24 1995 microchip technology inc. figure 4-7: pic16c72 register file map indf (1) tmr0 pcl status fsr porta portb portc pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con adres adcon0 indf (1) option pcl status fsr trisa trisb trisc pclath intcon pie1 pcon pr2 sspadd sspstat adcon1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register general purpose register 7fh ffh bank 0 bank 1 file address bfh c0h unimplemented data memory locations, read as '0'. note 1: not a physical register. file address figure 4-8: pic16c73/73a/74/74a register file map indf (1) tmr0 pcl status fsr porta portb portc portd (2) porte (2) pclath intcon pir1 pir2 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con rcsta txreg rcreg ccpr2l ccpr2h ccp2con adres adcon0 indf (1) option pcl status fsr trisa trisb trisc trisd (2) trise (2) pclath intcon pie1 pie2 pcon pr2 sspadd sspstat txsta spbrg adcon1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register general purpose register 7fh ffh bank 0 bank 1 file address file address unimplemented data memory locations, read as '0'. note 1: not a physical register. 2: these registers are not physically imple- mented on the pic16c73/73a, read as '0'.
1995 microchip technology inc. ds30390b-page 25 pic16c7x 4.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. the special function registers can be classi?d into two sets (core and peripheral). those registers associated with the ?ore?functions are described in this section, and those related to the operation of the peripheral fea- tures are described in the section of that peripheral fea- ture. table 4-1: PIC16C70/71/71a special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets (1) bank 0 00h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (3) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 03h (3) status irp (5) rp1 (5) rp0 t o pd zdcc 0001 1xxx 000q quuu 04h (3) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read ---x xxxx ---u uuuu 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h unimplemented 08h adcon0 adcs1 adcs0 (6) chs1 chs0 go/done adif adon 00-0 0000 00-0 0000 09h (3) adres a/d result register xxxx xxxx uuuu uuuu 0ah (2,3) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (3) intcon gie adie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u bank 1 80h (3) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (3) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 83h (3) status irp (5) rp1 (5) rp0 t o pd zdcc 0001 1xxx 000q quuu 84h (3) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register ---1 1111 ---1 1111 86h trisb portb data direction control register 1111 1111 1111 1111 87h (4) pcon por bo r ---- --qq ---- --uu 88h adcon1 pcfg1 pcfg0 ---- --00 ---- --00 89h (3) adres a/d result register xxxx xxxx uuuu uuuu 8ah (2,3) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (3) intcon gie adie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ?? note 1: other (non power-up) resets include external reset through mclr and watchdog timer reset. 2: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: these registers can be addressed from either bank. 4: the pcon register is not physically implemented in the pic16c71, read as ?? 5: the irp and rp1 bits are reserved on the pic16c7x, always maintain these bits clear. 6: bit5 of adcon0 is a general purpose r/w bit for the pic16c71 only. for the PIC16C70/71a, this bit is unimplemented, read as '0'.
pic16c7x ds30390b-page 26 1995 microchip technology inc. table 4-2: pic16c72 special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets (3) bank 0 00h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 03h (1) status irp (4) rp1 (4) rp0 t o pd zdcc 0001 1xxx 000q quuu 04h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read --xx xxxx --uu uuuu 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h unimplemented 09h unimplemented 0ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 0dh unimplemented 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm register (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h unimplemented 19h unimplemented 1ah unimplemented 1bh unimplemented 1ch unimplemented 1dh unimplemented 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done adon 0000 00-0 0000 00-0 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: other (non power-up) resets include external reset through mclr and watchdog timer reset. 4: the irp and rp1 bits are reserved on the pic16c7x, always maintain these bits clear.
1995 microchip technology inc. ds30390b-page 27 pic16c7x bank 1 80h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (1) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 83h (1) status irp (4) rp1 (4) rp0 t o pd zdcc 0001 1xxx 000q quuu 84h (1) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h unimplemented 89h unimplemented 8ah (1,2) pclath write buffer for the upper 5 bits of the pc ---0 0000 ---0 0000 8bh (1) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 8dh unimplemented 8eh pcon por bo r ---- --qq ---- --uu 8fh unimplemented 90h unimplemented 91h unimplemented 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat d/a p s r/w ua bf --00 0000 --00 0000 95h unimplemented 96h unimplemented 97h unimplemented 98h unimplemented 99h unimplemented 9ah unimplemented 9bh unimplemented 9ch unimplemented 9dh unimplemented 9eh unimplemented 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 table 4-2: pic16c72 special function register summary (cont.d) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets (3) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: other (non power-up) resets include external reset through mclr and watchdog timer reset. 4: the irp and rp1 bits are reserved on the pic16c7x, always maintain these bits clear.
pic16c7x ds30390b-page 28 1995 microchip technology inc. table 4-3: pic16c73/73a/74/74a special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets (2) bank 0 00h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (4) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 03h (4) status irp (7) rp1 (7) rp0 t o pd zdcc 0001 1xxx 000q quuu 04h (4) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read --xx xxxx --uu uuuu 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h (5) portd portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 09h (5) porte re2 re1 re0 ---- -xxx ---- -uuu 0ah (1,4) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (4) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (3) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 ccp2if ---- ---0 ---- ---0 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg usart transmit data register 0000 0000 0000 0000 1ah rcreg usart receive data register 0000 0000 0000 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done adon 0000 00-0 0000 00-0 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ?? note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose con- tents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. 4: these registers can be addressed from either bank. 5: portd and porte are not physically implemented on the pic16c73/73a, read as ?? 6: brown-out reset is not implemented on the pic16c73 or the pic16c74, read as '0'. 7: the irp and rp1 bits are reserved on the pic16c7x, always maintain these bits clear.
1995 microchip technology inc. ds30390b-page 29 pic16c7x bank 1 80h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (4) pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 83h (4) status irp (7) rp1 (7) rp0 t o pd zdcc 0001 1xxx 000q quuu 84h (4) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h (5) trisd portd data direction register 1111 1111 1111 1111 89h (5) trise ibf obf ibov pspmode trise2 trise1 trise0 0000 -111 0000 -111 8ah (1,4) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (4) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 pspie (3) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 ccp2ie ---- ---0 ---- ---0 8eh pcon por bo r (6) ---- --qq ---- --uu 8fh unimplemented 90h unimplemented 91h unimplemented 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat d/a p s r/w ua bf --00 0000 --00 0000 95h unimplemented 96h unimplemented 97h unimplemented 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 9ah unimplemented 9bh unimplemented 9ch unimplemented 9dh unimplemented 9eh unimplemented 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 table 4-3: pic16c73/73a/74/74a special function register summary (cont.d) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as ?? note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose con- tents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. 4: these registers can be addressed from either bank. 5: portd and porte are not physically implemented on the pic16c73/73a, read as ?? 6: brown-out reset is not implemented on the pic16c73 or the pic16c74, read as '0'. 7: the irp and rp1 bits are reserved on the pic16c7x, always maintain these bits clear.
pic16c7x ds30390b-page 30 1995 microchip technology inc. 4.2.2.1 status register the status register, shown in figure 4-9, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the t o and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). applicable devices 70 71 71a 72 73 73a 74 74a it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register because these instructions do not affect the z, c or dc bits from the status register. for other instructions, not affecting any status bits, see the "instruction set summary." note 1: bits irp and rp1 (status<7:6>) are not used by the pic16c7x and should be maintained clear. use of these bits as general purpose r/w bits is not recom- mended, since this may affect upward compatibility with future products. note 2: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. figure 4-9: status register (address 03h, 83h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 t o pd z dc c r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: irp : register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) the irp bit is reserved on the pic16c7x, always maintain this bit clear. bit 6-5: rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes. the rp1 bit is reserved on the pic16c7x, always maintain this bit clear. bit 4: t o : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions)(for borrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c : carry/borrow bit ( addwf , addlw,sublw,subwf instructions) 1 = a carry-out from the most signi?ant bit of the result occurred 0 = no carry-out from the most signi?ant bit of the result occurred note: for borrow the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
1995 microchip technology inc. ds30390b-page 31 pic16c7x 4.2.2.2 option register the option register is a readable and writable regis- ter which contains various control bits to con?ure the tmr0/wdt prescaler, the external int interrupt, tmr0, and the weak pull-ups on portb. applicable devices 70 71 71a 72 73 73a 74 74a note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer by setting bit psa (option<3>). figure 4-10: option register (address 81h) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6: intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16c7x ds30390b-page 32 1995 microchip technology inc. 4.2.2.3 intcon register the intcon register is a readable and writable regis- ter which contains various enable and ?g bits for the tmr0 register over?w, rb port change and external rb0/int pin interrupts. applicable devices 70 71 71a 72 73 73a 74 74a note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). figure 4-11: intcon register for PIC16C70/71/71a (address 0bh, 8bh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie adie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit (1) 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6: adie : a/d converter interrupt enable bit 1 = enables a/d interrupt 0 = disables a/d interrupt bit 5: t0ie : tmr0 over?w interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: inte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3: rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if : tmr0 over?w interrupt flag bit 1 = tmr0 register has over?wed (must be cleared in software) 0 = tmr0 register did not over?w bit 1: intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0: rbif : rb port change interrupt flag bit 1 = when at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state note 1: for the pic16c71 only, if an interrupt occurs while the gie bit is being cleared, the gie bit may be unin- tentionally re-enabled by the retfie instruction in the users interrupt service routine. refer to section 14.5 for a detailed description.
1995 microchip technology inc. ds30390b-page 33 pic16c7x figure 4-12: intcon register for pic16c72/73/73a/74/74a (address 0bh, 8bh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit (1) 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6: peie : peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5: t0ie : tmr0 over?w interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: inte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3: rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if : tmr0 over?w interrupt flag bit 1 = tmr0 register has over?wed (must be cleared in software) 0 = tmr0 register did not over?w bit 1: intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0: rbif : rb port change interrupt flag bit 1 = when at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state note 1: for the pic16c73 and pic16c74 only, if an interrupt occurs while the gie bit is being cleared, the gie bit may be unintentionally re-enabled by the retfie instruction in the users interrupt service routine. refer to section 14.5 for a detailed description.
pic16c7x ds30390b-page 34 1995 microchip technology inc. 4.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. applicable devices 70 71 71a 72 73 73a 74 74a note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. figure 4-13: pie1 register pic16c72 (address 8ch) u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adie sspie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6: adie : a/d converter interrupt enable bit 1 = enables the a/d converter interrupt 0 = disables the a/d converter interrupt bit 5-4: unimplemented : read as '0' bit 3: sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 over?w interrupt enable bit 1 = enables the tmr1 over?w interrupt 0 = disables the tmr1 over?w interrupt
1995 microchip technology inc. ds30390b-page 35 pic16c7x figure 4-14: pie1 register pic16c73/73a/74/74a (address 8ch) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: pspie (1) : parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6: adie : a/d converter interrupt enable bit 1 = enables the a/d converter interrupt 0 = disables the a/d converter interrupt bit 5: rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4: txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3: sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 over?w interrupt enable bit 1 = enables the tmr1 over?w interrupt 0 = disables the tmr1 over?w interrupt note 1: pic16c73 and pic16c73a devices do not have a parallel slave port implemented, this bit location is reserved on these two devices, always maintain this bit clear.
pic16c7x ds30390b-page 36 1995 microchip technology inc. 4.2.2.5 pir1 register this register contains the individual ?g bits for the peripheral interrupts. applicable devices 70 71 71a 72 73 73a 74 74a note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt ?g bits are clear prior to enabling an interrupt. figure 4-15: pir1 register pic16c72 (address 0ch) u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adif sspif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6: adif : a/d converter interrupt flag bit 1 = an a/d conversion completed 0 = the a/d conversion is not complete bit 5-4: unimplemented : read as '0' bit 3: sspif : synchronous serial port interrupt flag bit 1 = the transmission/reception is complete 0 = waiting to transmit/receive bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 over?w interrupt flag bit 1 = tmr1 register over?wed (must be cleared in software) 0 = tmr1 register did not over?w
1995 microchip technology inc. ds30390b-page 37 pic16c7x figure 4-16: pir1 register pic16c73/73a/74/74a (address 0ch) r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: pspif (1) : parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6: adif : a/d converter interrupt flag bit 1 = an a/d conversion completed 0 = the a/d conversion is not complete bit 5: rcif : usart receive interrupt flag bit 1 = the usart receive buffer is full 0 = the usart receive buffer is empty bit 4: txif : usart transmit interrupt flag bit 1 = the usart transmit buffer is empty 0 = the usart transmit buffer is full bit 3: sspif : synchronous serial port interrupt flag bit 1 = the transmission/reception is complete 0 = waiting to transmit/receive bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 over?w interrupt flag bit 1 = tmr1 register over?wed (must be cleared in software) 0 = tmr1 register did not over?w note 1: pic16c73 and pic16c73a devices do not have a parallel slave port implemented, this bit location is reserved on these two devices, always maintain this bit clear.
pic16c7x ds30390b-page 38 1995 microchip technology inc. 4.2.2.6 pie2 register this register contains the individual enable bit for the ccp2 peripheral interrupt. figure 4-17: pie2 register (address 8dh) applicable devices 70 71 71a 72 73 73a 74 74a u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ccp2ie r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-1: unimplemented: read as '0' bit 0: ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt
1995 microchip technology inc. ds30390b-page 39 pic16c7x 4.2.2.7 pir2 register this register contains the ccp2 interrupt ?g bit. applicable devices 70 71 71a 72 73 73a 74 74a . note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt ?g bits are clear prior to enabling an interrupt. figure 4-18: pir2 register (address 0dh) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ccp2if r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-1: unimplemented: read as '0' bit 0: ccp2if : ccp2 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused
pic16c7x ds30390b-page 40 1995 microchip technology inc. 4.2.2.8 pcon register the power control (pcon) register contains a ?g bit to allow differentiation between a power-on reset (por) to an external mclr reset or wdt reset. it also contains a status bit to determine if a brown-out reset (bor) occurred. applicable devices 70 71 71a 72 73 73a 74 74a note: bo r is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bo r is clear, indicating a brown-out has occurred. the bo r status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the boden bit in the con?uration word). figure 4-19: pcon register (address 8eh) u-0 u-0 u-0 u-0 u-0 u-0 r/w-q r/w-q por bo r (1) r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0: bo r (1) : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) note 1: brown-out reset is not implemented on the pic16c73/74.
1995 microchip technology inc. ds30390b-page 41 pic16c7x 4.3 pcl and pcla th the program counter (pc) is 13-bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<12:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 4-20 shows the two situations for the loading of the pc. the upper example in the ?ure shows how the pc is loaded on a write to pcl (pclath<4:0> ? pch). the lower exam- ple in the ?ure shows how the pc is loaded during a call or goto instruction (pclath<4:3> ? pch). figure 4-20: loading of pc in different situations 4.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 byte block). refer to the application note ?mplementing a table read" (an556). 4.3.2 stack the pic16cxx family has an 8 level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the ?st push. the tenth push overwrites the second push (and so on). applicable devices 70 71 71a 72 73 73a 74 74a pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu result goto, call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination 4.4 pr ogram memor y p a ging the pic16c73/73a and the pic16c74/74a have 4k of program memory, but the call and goto instructions only have a 11-bit address range. this 11-bit address range allows a branch within a 2k program memory page size. to allow call and goto instructions to address the entire 4k program memory address range, there must be another bit to specify the program mem- ory page. this paging bit comes from the pclath<3> bit (figure 4-20). when doing a call or goto instruc- tion, the user must ensure that this page bit (pclath<3>) is programmed so that the desired pro- gram memory page is addressed. if a return from a call instruction (or interrupt) is executed, the entire 13-bit pc is pushed onto the stack. therefore, manip- ulation of the pclath<3> is not required for the return instructions (which pops the address from the stack). note 1: there are no status bits to indicate stack over?w or stack under?w conditions. note 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw, and retfie instructions, or the vectoring to an inter- rupt address. applicable devices 70 71 71a 72 73 73a 74 74a note 1: the PIC16C70/71/71a/72 ignore both paging bits (pclath<4:3>, which are used to access program memory when more than one page is available. the use of pclath<4:3> as general purpose read/write bits for the pic16c7x is not recommended since this may affect upward compatibility with future products. the pic16c73/73a/74/74a ignores pag- ing bit (pclath<4>), which is used to access program memory pages 2 and 3 (1000h - 1fffh). the use of pclath<4> as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products.
pic16c7x ds30390b-page 42 1995 microchip technology inc. example 4-1 shows the calling of a subroutine in page 1 of the program memory. this example assumes that pclath is saved and restored by the interrupt ser- vice routine (if interrupts are used). example 4-1: call of a subroutine in page 1 from page 0 org 0x500 bsf pclath,3 ;select page 1 (800h-fffh) call sub1_p1 ;call subroutine in : ;page 1 (800h-fffh) : : org 0x900 sub1 p1: ;called subroutine : ;page 1 (800h-fffh) : return ;return to call subroutine ;in page 0 (000h-7ffh) 4.5 i ndirect ad dressing, indf and fsr register s the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses the register pointed to by the file select reg- ister, fsr. reading the indf register itself indirectly (fsr = '0') will read 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 4-21. however, irp is not used in the pic16c7x. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 4-2. example 4-2: indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue : ;yes continue applicable devices 70 71 71a 72 73 73a 74 74a figure 4-21: direct/indirect addressing for register ?e map detail see figure 4-5, figure 4-6, figure 4-7, and figure 4-8. note 1: the rp1 and irp bits are reserved, always maintain these bits clear. data memory indirect addressing direct addressing bank select location select (1) rp1 rp0 6 0 from opcode irp (1) fsr register 7 0 bank select location select 00 01 10 11 00h 7fh 00h 7fh bank 0 bank 1 bank 2 bank 3 not used
1995 microchip technology inc. ds30390b-page 43 pic16c7x 5.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. 5.1 por t a and t risa register s porta is a 5-bit latch for PIC16C70/71/71a. porta is a 6-bit latch for pic16c72/73/73a/74/74a. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. all pins have data direction bits (tris registers) which can con?ure these pins as output or input. setting a trisa register bit puts the corresponding out- put driver in a hi-impedance mode. clearing a bit in the trisa register puts the contents of the output latch on the selected pin(s). reading the porta register reads the status of the pins whereas writing to it will write to the port latch. all write operations are read-modify-write operations. applicable devices 70 71 71a 72 73 73a 74 74a applicable devices 70 71 71a 72 73 73a 74 74a therefore a write to a port implies that the port pins are read, this value is modi?d, and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. other porta pins are multiplexed with analog inputs and analog v ref input. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 5-1: initializing porta clrf porta ; initialize porta by ; setting output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6> are always ; read as '0'. note: on a power-on reset, these pins are con- ?ured as analog inputs and read as '0'. figure 5-1: block diagram of ra3:ra0 and ra5 pins data bus wr port wr tris rd port data latch tris latch p v ss i/o pin to a/d converter note: i/o pin has protection diodes to v dd and v ss . the PIC16C70/71/71/a devices do not have a pin ra5. q d q ck q d q ck en qd en n analog input mode ttl input buffer v dd rd tris this document was created with framemake r404
pic16c7x ds30390b-page 44 1995 microchip technology inc. figure 5-2: block diagram of ra4/t0cki pin table 5-1: porta functions table 5-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit0 ttl input/output or analog input ra1/an1 bit1 ttl input/output or analog input ra2/an2 bit2 ttl input/output or analog input ra3/an3/v ref bit3 ttl input/output or analog input/v ref ra4/t0cki bit4 st input/output or external clock input for timer0 output is open drain type ra5/an4/ss (1) bit5 ttl input/output, slave select input for synchronous serial port, or analog input legend: ttl = ttl input, st = schmitt trigger input note 1: the PIC16C70/71/71a does not have porta<5> or trisa<5>, read as '0'. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 05h porta ra5 (1) ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu 85h trisa trisa5 (1) trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 9fh adcon1 pcfg2 (2) pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. note 1: porta<5> and trisa<5> are not implemented on the PIC16C70/71/71a. 2: bit pcfg2 is not implemented on the PIC16C70/71/71a. data bus wr port wr tris rd port data latch tris latch schmitt trigger input buffer n v ss tmr0 clock input note: i/o pin has protection diodes to v ss only. q d q ck q d q ck en qd en rd tris ra4/t0cki pin
1995 microchip technology inc. ds30390b-page 45 pic16c7x 5.2 p or tb and trisb register s portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisb. setting a bit in the trisb register puts the corresponding output driver in a hi-impedance input mode. clearing a bit in the trisb register puts the contents of the output latch on the selected pin(s). example 5-2: initializing portb clrf portb ; initialize portb by ; setting output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is done by clearing bit rbpu (option<7>). the weak pull-up is automatically turned off when the port pin is con?ured as an output. the pull-ups are disabled on a power-on reset. figure 5-3: block diagram of rb3:rb0 pins four of portbs pins, rb7:rb4, have an interrupt on change feature. only pins con?ured as inputs can cause this interrupt to occur (i.e. any rb7:rb4 pin con- ?ured as an output is excluded from the interrupt on change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of applicable devices 70 71 71a 72 73 73a 74 74a data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer note 1: i/o pins have diode protection to v dd and v ss . 2: trisb = '1' enables weak pull-up if rbpu = '0' (option<7>). schmitt trigger buffer tris latch portb. the ?ismatch?outputs of rb7:rb4 are or?d together to generate the rb port change inter- rupt with ?g bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear ?g bit rbif. a mismatch condition will continue to set ?g bit rbif. reading portb will end the mismatch condition, and allow ?g bit rbif to be cleared. this interrupt on mismatch feature, together with soft- ware con?urable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression. refer to the embedded control handbook, "implementing wake-up on key stroke" (an552). the interrupt on change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt on change feature. figure 5-4: block diagram of rb7:rb4 pins note: for the pic16c71/73/74 only, if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then interrupt ?g bit rbif may not get set. data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: trisb = '1' enables weak pull-up if rbpu = '0' (option<7>). st buffer rb7:rb6 in serial programming mode
pic16c7x ds30390b-page 46 1995 microchip technology inc. table 5-3: portb functions table 5-4: summary of registers associated with portb name bit# buffer function rb0/int bit0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
1995 microchip technology inc. ds30390b-page 47 pic16c7x 5.3 por tc and trisc register s portc is an 8-bit bi-directional port. each pin is indi- vidually con?urable as an input or output through the trisc register. portc is multiplexed with several peripheral functions (table 5-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in de?ing tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. the tris bit override is in effect only while the peripheral is enabled. the user should refer to the corresponding peripheral section for the correct tris bit settings. applicable devices 70 71 71a 72 73 73a 74 74a example 5-3: initializing portc clrf portc ; initialize portc by ; setting output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs figure 5-5: portc block diagram (peripheral output override) data latch tris latch rd tris p v ss q d q ck q d q ck en qd en n v dd 0 1 rd port wr port wr tris schmitt trigger peripheral input peripheral oe (2) data bus port/peripheral select (1) peripheral data-out rd port note 1: port/peripheral select signal selects between port data and peripheral output. 2: peripheral oe (output enable) is only activated if peripheral select is active. 3: i/o pins have diode protection to v dd and v ss . i/o pin
pic16c7x ds30390b-page 48 1995 microchip technology inc. table 5-5: portc functions table 5-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t1cki bit0 st input/output port pin or timer1 oscillator output/timer1 clock input rc1/t1osi/ccp2 (1) bit1 st input/output port pin, timer1 oscillator input, capture2 input/compare2 output/pwm2 output rc2/ccp1 bit2 st input/output port pin or capture1 input/compare1 output/pwm1 output rc3/sck/scl bit3 st rc3/sck/scl can also be selected as the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit4 st rc4/sdi/sda can also be selected as the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output rc6/tx/ck (2) bit6 st input/output port pin, usart asynchronous transmit, or usart syn- chronous clock rc7/rx/dt (2) bit7 st input/output port pin usart asynchronous receive, or usart syn- chronous data legend: st = schmitt trigger input note 1: the ccp2 multiplexed function is not enabled on the pic16c72. 2: the tx/ck and rx/dt multiplexed functions are not enabled on the pic16c72. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: x = unknown, u = unchanged.
1995 microchip technology inc. ds30390b-page 49 pic16c7x 5.4 por td and trisd register s portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually con?urable as an input or output. applicable devices 70 71 71a 72 73 73a 74 74a portd can be con?ured as an 8-bit wide micropro- cessor port (or parallel slave port) by setting control bit pspmode (trise<4>). in this mode, the input buffers are ttl. figure 5-6: portd block diagram (in i/o port mode) table 5-7: portd functions name bit# buffer type function rd0/psp0 bit0 st/ttl (1) input/output port pin or parallel slave port bit0 rd1/psp1 bit1 st/ttl (1) input/output port pin or parallel slave port bit1 rd2/psp2 bit2 st/ttl (1) input/output port pin or parallel slave port bit2 rd3/psp3 bit3 st/ttl (1) input/output port pin or parallel slave port bit3 rd4/psp4 bit4 st/ttl (1) input/output port pin or parallel slave port bit4 rd5/psp5 bit5 st/ttl (1) input/output port pin or parallel slave port bit5 rd6/psp6 bit6 st/ttl (1) input/output port pin or parallel slave port bit6 rd7/psp7 bit7 st/ttl (1) input/output port pin or parallel slave port bit7 legend: st = schmitt trigger input ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffer when in parallel slave port mode. data bus wr port wr tris rd port data latch tris latch schmitt trigger input buffer note: i/o pins has protection diodes to v dd and v ss . q d q ck q d q ck en qd en i/o pin rd tris
pic16c7x ds30390b-page 50 1995 microchip technology inc. table 5-8: summary of registers associated with portd address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 08h portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 88h trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 1111 1111 1111 1111 89h trise ibf obf ibov pspmode trise2 trise1 trise0 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by portd.
1995 microchip technology inc. ds30390b-page 51 pic16c7x 5.5 por te and trise register porte has three pins re0/rd /an5, re1/wr /an6 and re2/cs /an7, which are individually con?urable as inputs or outputs. these pins have schmitt trigger input buffers. i/o porte becomes control inputs for the micropro- cessor port when bit pspmode (trise<4>) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are con?ured as digital inputs) and that register adcon1 is con?ured for dig- ital i/o. in this mode the input buffers are ttl. applicable devices 70 71 71a 72 73 73a 74 74a figure 5-7 shows the trise register, which also con- trols the parallel slave port operation. porte pins are multiplexed with analog inputs. the operation of these pins is selected by control bits in the adcon1 register. when selected as an analog input, these pins will read as '0's. trise controls the direction of the re pins, even when they are being used as analog inputs. the user must make sure to keep the pins con?ured as inputs when using them as analog inputs. note: on a power-on reset these pins are con- ?ured as analog inputs. figure 5-7: trise register (address 89h) r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode trise2 trise1 trise0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: ibf: input buffer full status bit 1 = a word has been received and waiting to be read by the cpu 0 = no word has been received bit 6: obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5: ibov : input buffer over?w detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no over?w occurred bit 4: pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3: unimplemented : read as '0' bit 2: trise2 : direction control bit for pin re2/cs /an7 1 = input 0 = output bit 1: trise1 : direction control bit for pin re1/wr /an6 1 = input 0 = output bit 0: trise0 : direction control bit for pin re0/rd /an5 1 = input 0 = output
pic16c7x ds30390b-page 52 1995 microchip technology inc. figure 5-8: porte block diagram (in i/o port mode) table 5-9: porte functions table 5-10: summary of registers associated with porte name bit# buffer type function re0/rd /an5 bit0 st/ttl (1) input/output port pin, read control input in parallel slave port mode, or analog input: rd 1 = not a read operation 0 = read operation. reads portd register (if chip selected) re1/wr /an6 bit1 st/ttl (1) input/output port pin, write control input in parallel slave port mode, or analog input: wr 1 = not a write operation 0 = write operation. writes portd register (if chip selected) re2/cs /an7 bit2 st/ttl (1) input/output port pin, chip select control input in parallel slave port mode, or analog input: cs 1 = device is not selected 0 = device is selected legend: st = schmitt trigger input ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffer when in parallel slave port mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 09h porte re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode trise2 trise1 trise0 0000 -111 0000 -111 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by porte. data bus wr port wr tris rd port data latch tris latch schmitt trigger input buffer q d q ck q d q ck en qd en i/o pin rd tris
1995 microchip technology inc. ds30390b-page 53 pic16c7x 5.6 i/o pr ogramming considerations 5.6.1 bi-directional i/o ports any instruction which writes, operates internally as a read followed by a write operation. the bcf and bsf instructions, for example, read the register into the cpu, execute the bit operation and write the result back to the register. caution must be used when these instructions are applied to a port with both inputs and outputs de?ed. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu. then the bsf operation takes place on bit5 and portb is written to the output latches. if another bit of portb is used as a bi-directional i/o pin (e.g., bit0) and it is de?ed as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched to an output, the content of the data latch may now be unknown. reading the port register, reads the values of the port pins. writing to the port register writes the value to the port latch. when using read-modify-write instructions (ex. bcf, bsf , etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. example 5-4 shows the effect of two sequential read- modify-write instructions on an i/o port. applicable devices 70 71 71a 72 73 73a 74 74a example 5-4: read-modify-write instructions on an i/o port ;initial port settings: portb<7:4> inputs ; portb<3:0> outputs ;portb<7:6> have external pull-ups and are ;not connected to other circuitry ; ; port latch port pins ; ---------- --------- bcf portb, 7 ; 01pp ppp 11pp ppp bcf portb, 6 ; 10pp ppp 11pp ppp bsf status, rp0 ; bcf trisb, 7 ; 10pp ppp 11pp ppp bcf trisb, 6 ; 10pp ppp 10pp ppp ; ;note that the user may have expected the ;pin values to be 00pp ppp. the 2nd bcf ;caused rb7 to be latched as the pin value ;(high). a pin actively outputting a low or high should not be driven from external devices at the same time in order to change the level on this pin (?ired-or? ?ired-and?. the resulting high output currents may damage the chip. 5.6.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5- 9). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that ?e to be read into the cpu is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 5-9: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb7:rb0 movwf portb write to portb nop port pin sampled here nop movf portb,w instruction executed movwf portb write to portb nop movf portb,w pc t pd note: this example shows a write to portb followed by a read from portb. note that: data setup time = (0.25t cy - t pd ) where t cy = instruction cycle t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be prob- lematic.
pic16c7x ds30390b-page 54 1995 microchip technology inc. 5.7 p arallel sla ve p or t portd operates as an 8-bit wide parallel slave port, or microprocessor port when control bit pspmode (trise<4>) is set. in slave mode it is asynchronously readable and writable by the external world through r d control input pin re0/rd /an5 and wr control input pin re1/wr /an6. it can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd /an5 to be the rd input, re1/wr /an6 to be the wr input and re2/cs /an7 to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be con?ured as inputs (set) and the a/d port con?uration bits pcfg2:pcfg0 (adcon1<2:0> must be set, which will con?ure pins re2:re0 as digital i/o. there are actually two 8-bit latches, one for data-out (from the pic16/17) and one for data input. the user writes 8-bit data to portd data latch and reads data from the port pin latch (note that they have the same applicable devices 70 71 71a 72 73 73a 74 74a address). in this mode, the trisd register is ignored, since the microprocessor is controlling the direction of data ?w. input buffer full status flag bit ibf (trise<7>), is set if a received word is waiting to be read by the cpu. once the portd input latch is read, ibf is cleared. ibf is a read only status bit. output buffer full status flag bit obf (trise<6>), is set if a word written to portd latch is waiting to be read by the external bus. once the portd output latch is read by the microprocessor, obf is cleared. input buffer over?w status flag bit ibov (trise<5>) is set if a second write to the micro- processor port is attempted when the previous word has not been read by the cpu (the ?st word is retained in the buffer). when not in parallel slave port mode, the ibf and obf bits are held clear. however, if ?g bit ibov was previ- ously set, it must be cleared in the software. an interrupt is generated and latched into ?g bit pspif (pir1<7>) when a read or a write operation is completed. interrupt ?g bit pspif must be cleared by user software and the interrupt can be disabled by clearing interrupt enable bit pspie (pie1<7>). figure 5-10: portd and porte block diagram (parallel slave port) en d q ck data bus wr port rd port one bit of portd set interrupt ?g pspif (pir1<7>) rdx pin ttl ttl read chip select write rd cs wr note: i/o pins has protection diodes to v dd and v ss . en dq en
1995 microchip technology inc. ds30390b-page 55 pic16c7x table 5-11: registers associated with parallel slave port address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 08h portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 09h porte re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode trise2 trise1 trise0 0000 -111 0000 -111 0ch pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the parallel slave port.
pic16c7x ds30390b-page 56 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30390b-page 57 pic16c7x 6.0 overview of timer modules the PIC16C70 and pic16c71/71a have one timer module. the pic16c72, pic16c73/73a and pic16c74/74a have three timer modules. each module can generate an interrupt to indicate that an event has occurred (i.e. timer over?w). each of these modules is explained in full detail in the following sections. the timer modules are: timer0 module (section 7.0) timer1 module (section 8.0) timer2 module (section 9.0) 6.1 timer0 over vie w the timer0 module (previously known as rtcc) is a simple 8-bit over?w counter. the clock source can be either the internal system clock (fosc/4) or an external clock. when the clock source is an external clock, the timer0 module can be selected to increment on either the rising or falling edge. the timer0 module also has a programmable pres- caler option. this prescaler can be assigned to either the timer0 module or the watchdog timer. bit psa (option<3>) assigns the prescaler, and bits ps2:ps0 (option<2:0>) determine the prescaler value. timer0 can increment at the following rates: 1:1 (when pres- caler assigned to watchdog timer), 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, and 1:256 (timer0 only). synchronization of the external clock occurs after the prescaler. when the prescaler is used, the external clock frequency may be higher then the devices fre- quency. the maximum frequency is 50 mhz, given the high and low time requirements of the clock. 6.2 timer 1 over vie w timer1 is a 16-bit timer/counter. the clock source can be either the internal system clock (fosc/4), an external clock, or an external crystal. timer1 can operate as either a timer or a counter. when operating as a counter (external clock source), the counter can either operate synchronized to the device or asynchronously to the device. asynchronous operation allows timer1 to operate during sleep, which is useful for applications that require a real-time clock as well as the power sav- ings of sleep mode. timer1 also has a prescaler option which allows timer1 to increment at the following rates: 1:1, 1:2, 1:4, and 1:8. timer1 can be used in conjunction with the applicable devices 70 71 71a 72 73 73a 74 74a applicable devices 70 71 71a 72 73 73a 74 74a applicable devices 70 71 71a 72 73 73a 74 74a capture/compare/pwm module. when used with a ccp module, timer1 is the time-base for 16-bit capture or the 16-bit compare and must be synchronized to the device. 6.3 timer2 over vie w timer2 is an 8-bit timer with a programmable prescaler and postscaler, as well as an 8-bit period register (pr2). timer2 can be used with the ccp1 module (in pwm mode) as well as the baud rate generator for the synchronous serial port (ssp). the prescaler option allows timer2 to increment at the following rates: 1:1, 1:4, 1:16. the postscaler allows the tmr2 register to match the period register (pr2) a programmable number of times before generating an interrupt. the postscaler can be programmed from 1:1 to 1:16 (inclusive). 6.4 ccp o ver vie w the ccp module(s) can operate in one of these three modes: 16-bit capture, 16-bit compare, or up to 10-bit pulse width modulation (pwm). capture mode captures the 16-bit value of tmr1 into the ccprxh:ccprxl register pair. the capture event can be programmed for either the falling edge, rising edge, fourth rising edge, or the sixteenth rising edge of the ccpx pin. compare mode compares the tmr1h:tmr1l register pair to the ccprxh:ccprxl register pair. when a match occurs an interrupt can be generated, and the output pin ccpx can be forced to given state (high or low), tmr1 can be reset (ccp1), or timer1 reset and start a/d conversion (ccp2). this depends on the con- trol bits ccpxm3:ccpxm0. pwm mode compares the tmr2 register to a 10-bit duty cycle register (ccprxh:ccprxl<5:4>) as well as to an 8-bit period register (pr2). when the tmr2 reg- ister = duty cycle register, the ccpx pin will be forced low. when tmr2 = pr2, tmr2 is cleared to 00h, an interrupt can be generated, and the ccpx pin (if an out- put) will be forced high. applicable devices 70 71 71a 72 73 73a 74 74a applicable devices 70 71 71a 72 73 73a 74 74a this document was created with framemake r404
pic16c7x ds30390b-page 58 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30390b-page 59 pic16c7x 7.0 timer0 module the timer0 module timer/counter has the following fea- tures: 8-bit timer/counter readable and writable 8-bit software programmable prescaler internal or external clock select interrupt on over?w from ffh to 00h edge select for external clock figure 7-1 is a simpli?d block diagram of the timer0 module. timer mode is selected by clearing bit t0cs (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles (figure 7-2 and figure 7-3). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option<5>). in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 applicable devices 70 71 71a 72 73 73a 74 74a source edge select bit t0se (option<4>). clearing bit t0se selects the rising edge. restrictions on the external clock input are discussed in detail in section 7.2. the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the pres- caler assignment is controlled in software by the control bit psa (option<3>). clearing bit psa will assign the prescaler to the timer0 module. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. section 7.3 details the operation of the prescaler. 7.1 timer0 in terrupt the tmr0 interrupt is generated when the tmr0 reg- ister over?ws from ffh to 00h. this over?w sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut off during sleep. see figure 7-4 for timer0 interrupt timing. applicable devices 70 71 71a 72 73 73a 74 74a figure 7-1: timer0 block diagram figure 7-2: timer0 timing: internal clock/no prescale note 1: t0cs, t0se, psa, ps2:ps0 (option<5:0>). 2: the prescaler is shared with watchdog timer (refer to figure 7-6 for detailed block diagram). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 psout (2 cycle delay) psout data bus 8 psa ps2, ps1, ps0 set interrupt ?g bit t0if on over?w 3 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 t0 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed this document was created with framemake r404
pic16c7x ds30390b-page 60 1995 microchip technology inc. figure 7-3: timer0 timing: internal clock/prescale 1:2 figure 7-4: timer0 interrupt timing pc+6 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clkout (3) timer0 t0if bit (intcon<2>) feh gie bit (intcon<7>) instruction pc instruction fetched pc pc +1 pc +1 0004h 0005h instruction executed inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dummy cycle dummy cycle ffh 00h 01h 02h note 1: interrupt ?g bit t0if is sampled here (every q1). 2: interrupt latency = 4tcy where tcy = instruction cycle time. 3: clkout is available only in rc oscillator mode. f low
1995 microchip technology inc. ds30390b-page 61 pic16c7x 7.2 using timer0 with an external cloc k when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 7.2.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 7-5). therefore, it is necessary for t0cki to be high for at least 2tosc (and a small rc delay of 20 ns) and low for at least 2tosc (and a small rc delay of 20 ns). refer to the electrical speci?ation of the desired device. applicable devices 70 71 71a 72 73 73a 74 74a when a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres- caler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. there- fore, it is necessary for t0cki to have a period of at least 4tosc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the mini- mum pulse width requirement of 10 ns. refer to param- eters 40, 41 and 42 in the electrical speci?ation of the desired device. 7.2.2 tmr0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 mod- ule is actually incremented. figure 7-5 shows the delay from the external clock edge to the timer incrementing. figure 7-5: timer0 timing with external clock q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 external clock input or prescaler output (2) external clock/prescaler output after sampling increment timer0 (q4) timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling note 1: delay from clock input change to timer0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval between two edges on timer0 input = 4tosc max. 2: external clock if no prescaler selected, prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs. (3) (1)
pic16c7x ds30390b-page 62 1995 microchip technology inc. 7.3 p re scaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer, respectively (figure 7-6). for simplicity, this counter is being referred to as ?rescaler?throughout this data sheet. note that there is only one prescaler available which is mutually exclusive between the timer0 module and the watchdog timer. thus, a pres- applicable devices 70 71 71a 72 73 73a 74 74a caler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice- versa. the psa and ps2:ps0 bits (option<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the pres- caler is not readable or writable. figure 7-6: block diagram of the timer0/wdt prescaler ra4/t0cki t0se pin m u x clkout (=fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set ?g bit t0if on over?w 8 psa t0cs
1995 microchip technology inc. ds30390b-page 63 pic16c7x 7.3.1 switching prescaler assignment the prescaler assignment is fully under software con- trol, i.e., it can be changed ?n the ??during program execution. example 7-1: changing prescaler (timer0 ? wdt) bcf status, rp0 ;bank 0 clrf tmr0 ;clear tmr0 & prescaler bsf status, rp0 ;bank 1 clrwdt ;clears wdt movlw b'xxxx1xxx' ;select new prescale movwf option ;value & wdt bcf status, rp0 ;bank 0 note: to avoid an unintended device reset, the following instruction sequence (shown in example 7-1) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled. to change prescaler from the wdt to the timer0 mod- ule use the sequence shown in example 7-2. example 7-2: changing prescaler (wdt ? timer0) clrwdt ;clear wdt and ;prescaler bsf status, rp0 ;bank 1 movlw b'xxxx0xxx' ;select tmr0, new ;prescale value and movwf option ;clock source bcf status, rp0 ;bank 0 table 7-1: registers associated with timer0, PIC16C70/71/71a table 7-2: registers associated with timer0, pic16c72/73/73a/74/74a address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 0bh/8bh intcon gie adie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0.
pic16c7x ds30390b-page 64 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30390b-page 65 pic16c7x 8.0 timer1 module the timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (tmr1h and tmr1l) which are readable and writable. the tmr1 register pair (tmr1h + tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on over?w which is latched in interrupt ?g bit tmr1if (pir1<0>). this interrupt can be enabled or disabled using tmr1 interrupt enable bit tmr1ie (pie1<0>). timer1 can operate in one of two modes: as a timer as a counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). applicable devices 70 71 71a 72 73 73a 74 74a in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input on pin rc0/t1oso/ t1cki. timer1 can be turned on and off using the control bit tmr1on (t1con<0>). timer1 also has an internal ?eset input? this reset can be generated by either of the two ccp modules (section 10.0). figure 8-1 shows the timer1 control register. for the pic16c72/73a/74a, when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi/ccp2 and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. for the pic16c73/74, when the timer1 oscillator is enabled (t1oscen is set), rc1/t1osi/ccp2 pin becomes an input, however the rc0/t1oso/t1cki pin will have to be con?ured as an input by setting the trisc<0> bit. figure 8-1: t1con: timer1 control register (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3: t1oscen : timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut off note: the oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 this bit is ignored. timer1 uses the external clock when tmr1cs = 0. bit 1: tmr1cs : timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (osc/4) bit 0: tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1 this document was created with framemake r404
pic16c7x ds30390b-page 66 1995 microchip technology inc. 8.1 timer1 oper ation in timer mode timer mode is selected by clearing the tmr1cs (t1con<1>) bit. in this mode, the input clock to the timer is osc/4. the synchronize control bit t1sync (t1con<2>) has no effect since the internal clock is always in sync. 8.2 timer1 operation in sync hr oniz ed counter mode counter mode is selected by setting bit tmr1cs. in this mode the timer increments on every rising edge of clock input on pin rc1/t1osi/ccp2 when bit t1oscen is set or pin rc0/t1oso/t1cki when bit t1oscen is cleared. if t1sync is cleared, then the external clock input is synchronized with internal phase clocks. the synchro- nization is done after the prescaler stage. the pres- caler stage is an asynchronous ripple-counter. in this con?uration, during sleep mode, timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. the pres- caler however will continue to increment. applicable devices 70 71 71a 72 73 73a 74 74a applicable devices 70 71 71a 72 73 73a 74 74a 8.2.1 external clock input timing for synchronized counter mode when an external clock input is used for timer1 in syn- chronized counter mode, it must meet certain require- ments. the external clock requirement is due to internal phase clock (tosc) synchronization. also, there is a delay in the actual incrementing of tmr1 after syn- chronization. when the prescaler is 1:1, the external clock input is the same as the prescaler output. the synchronization of t1cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t1cki to be high for at least 2tosc (and a small rc delay of 20 ns) and low for at least 2tosc (and a small rc delay of 20 ns). refer to the appropri- ate electrical speci?ations, parameters 45, 46, and 47. when a prescaler other than 1:1 is used, the external clock input is divided by the asynchronous ripple- counter type prescaler so that the prescaler output is symmetrical. in order for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. therefore, it is necessary for t1cki to have a period of at least 4tosc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t1cki high and low time is that they do not violate the minimum pulse width requirements of 10 ns). refer to the appropriate electrical speci?ations, parameters 40, 42, 45, 46, and 47. figure 8-2: timer1 block diagram tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) osc/4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rc0/t1oso/t1cki rc1/t1osi/ccp2 (2) note 1: when the t1oscen bit is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. 2: the ccp2 module is not implemented in the pic16c72. 3: for the pic16c73 and pic16c74, the schmitt trigger is not implemented in external clock mode. set ?g bit tmr1if on over?w tmr1 (3)
1995 microchip technology inc. ds30390b-page 67 pic16c7x 8.3 timer1 operation in asy nc hr onous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on over?w which will wake-up the processor. however, special precautions in soft- ware are needed to read/write the timer (section 8.3.2). in asynchronous counter mode, timer1 can not be used as a time-base for capture or compare opera- tions. 8.3.1 external clock input timing with unsynchronized clock if control bit t1sync is set, the timer will increment completely asynchronously. the input clock must meet a certain minimum high time and low time require- ments. refer to the appropriate electrical speci?a- tions section, timing parameters 45, 46, and 47. 8.3.2 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running, from an external asynchronous clock, will guarantee a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems since the timer may over?w between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers while the register is incrementing. this may produce an unpre- dictable value in the timer register. reading the 16-bit value requires some care. example 8-1 is an example routine to read the 16-bit timer value. this is useful if the timer cannot be stopped. applicable devices 70 71 71a 72 73 73a 74 74a example 8-1: reading a 16-bit free- running timer ; all interrupts are disabled movf tmr1h, w ;read high byte movwf tmph ; movf tmr1l, w ;read low byte movwf tmpl ; movf tmr1h, w ;read high byte subwf tmph, w ;sub 1st read ; with 2nd read btfsc status,z ;is result = 0 goto continue ;good 16-bit read ; ; tmr1l may have rolled over between the read ; of the high and low bytes. reading the high ; and low bytes now will read a good value. ; movf tmr1h, w ;read high byte movwf tmph ; movf tmr1l, w ;read low byte movwf tmpl ; ; re-enable the interrupt (if required) continue ;continue with your code 8.4 timer1 oscillator a crystal oscillator circuit is built in between t1osi pin (input) and t1oso (ampli?r output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. table 8-1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. applicable devices 70 71 71a 72 73 73a 74 74a table 8-1: capacitor selection for the timer1 oscillator osc type freq c1 c2 lp 32 khz (1) 100 khz 200 khz 15 pf 15 pf 0 - 15 pf 15 pf 15 pf 0 - 15 pf higher capacitance increases the stability of oscilla- tor but also increases the start-up time. these values are for design guidance only. note 1: for v dd > 4.5v, c1 = c2 ? 30 pf is recom- mended. crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm
pic16c7x ds30390b-page 68 1995 microchip technology inc. 8.5 resetting timer1 using a ccp t rig g er output the ccp2 module is not implemented on the pic16c72 device. if the ccp1 or ccp2 module is con?ured in compare mode to generate a ?pecial event trigger" (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1. timer1 must be con?ured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1 or ccp2, the write will take precedence. applicable devices 70 71 71a 72 73 73a 74 74a note: the special event triggers from the ccp1 and ccp2 modules will not set interrupt ?g bit tmr1if (pir1<0>). in this mode of operation, the ccprxh:ccprxl regis- ters pair effectively becomes the period register for timer1. 8.6 resetting of timer1 register p air ( tmr1h, tmr1l) tmr1h and tmr1l registers are not reset on a por or any other reset except by the ccp1 special event trigger. t1con register is reset to 00h on a power-on reset or a brown-out reset. in any other reset, the register is unaffected. 8.7 timer1 pres caler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. applicable devices 70 71 71a 72 73 73a 74 74a applicable devices 70 71 71a 72 73 73a 74 74a table 8-2: registers associated with timer1 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1,2) adif rcif (2) txif (2) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1,2) adie rcie (2) txie (2) sspie ccp1ie tmr21e tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1 s ync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by thetimer1 module. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. 2: the pic16c72 does not have a parallel slave port or a usart, these bits are unimplemented, read as '0'.
1995 microchip technology inc. ds30390b-page 69 pic16c7x 9.0 timer2 module timer2 is an 8-bit timer with a prescaler and a postscaler. it can be used as the pwm time-base for pwm mode of the ccp module(s). the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16 (selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the timer2 module has an 8-bit period register pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is set during reset. the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in ?g bit tmr2if, pir1<1>). timer2 can be shut off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. figure 9-2 shows the timer2 control register. applicable devices 70 71 71a 72 73 73a 74 74a 9.1 timer2 prescaler and p ostscaler the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, or watchdog timer reset) tmr2 will not clear when t2con is written, only for a wdt, por, and mclr reset. 9.2 output of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module which optionally uses it to generate shift clock. figure 9-1: timer2 block diagram applicable devices 70 71 71a 72 73 73a 74 74a applicable devices 70 71 71a 72 73 73a 74 74a comparator tmr2 sets ?g tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 osc/4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to this document was created with framemake r404
pic16c7x ds30390b-page 70 1995 microchip technology inc. figure 9-2: t2con: timer2 control register (address 12h) table 9-1: registers associated with timer2 as a timer/counter u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6-3: toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2: tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0: t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1,2) adif rcif (2) txif (2) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1,2) adie rcie (2) txie (2) sspie ccp1ie tmr21e tmr1ie 0000 0000 0000 0000 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer2 module. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. 2: the pic16c72 does not have a parallel slave port or a usart, these bits are unimplemented, read as '0'.
1995 microchip technology inc. ds30390b-page 71 pic16c7x 10.0 capture/compare/pwm module(s) each ccp (capture/compare/pwm) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a pwm out- put. both the ccp1 and ccp2 modules are identical in operation, with the exception of the operation of the special event trigger. table 10-1 and table 10-2 show the resources and interactions of the ccp module(s). in the following sections, the operation of a ccp mod- ule is described with respect to ccp1. ccp2 operates the same as ccp1, except where noted. applicable devices 70 71 71a 72 73 73a 74 74a ccp1 70 71 71a 72 73 73a 74 74a ccp2 ccp1 module: capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). both are readable and writable. ccp2 module: capture/compare/pwm register2 (ccpr2) is made up of two 8-bit registers: ccpr2l (low byte) and ccpr2h (high byte). both are readable and writable. for use of the ccp modules, refer to the embedded control handbook, "using the ccp modules" (an594). table 10-1: ccp mode - timer resource table 10-2: interaction of two ccp modules ccp mode timer resource capture compare pwm timer1 timer1 timer2 ccpx mode ccpy mode interaction capture capture same tmr1 timebase. capture compare the compare should be con?ured for the special event trigger, which clears tmr1. compare compare the compare(s) should be con?ured for the special event trigger, which clears tmr1. pwm pwm the pwms will have the same frequency, and update rate (tmr2 interrupt). pwm capture none pwm compare none this document was created with framemake r404
pic16c7x ds30390b-page 72 1995 microchip technology inc. figure 10-1: ccp1con register (address 17h)/ccp2con register (address 1dh) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ccpxx ccpxy ccpxm3 ccpxm2 ccpxm1 ccpxm0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: ccpxx:ccpxy : pwm high resolution, low order select bits capture mode: unused compare mode: unused pwm mode: write the two low order bits in high resolution (10-bit) mode. may be kept constant (at '0') if only 8-bit resolution (in standard resolution mode) is desired. bit 3-0: ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm off (resets ccpx module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccpxif bit is set) 1001 = compare mode, clear output on match (ccpxif bit is set) 1010 = compare mode, generate software interrupt on match (ccpxif bit is set, ccpx pin is unaffected) 1011 = compare mode, trigger special event (ccpxif bit is set; ccp1 resets tmr1; ccp2 resets tmr1 and starts an a/d conversion (if a/d module is enabled)) 11xx = pwm mode 10.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16- bit value of the tmr1 register when an event occurs on pin rc2/ccp1. an event is de?ed as: a falling edge a rising edge every 4th rising edge every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request ?g bit ccp1if (pir1<2>) is set. it must be reset in software. if another capture occurs before the value in register ccpr1 is read, the old captured value will be lost. in capture mode, the rc2/ccp1 pin should be con?ured as an input by setting its corre- sponding tris bit. applicable devices 70 71 71a 72 73 73a 74 74a when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the ?g bit ccp1if following any such change in operating mode. note: if the rc2/ccp1 is con?ured as an out- put, a write to the port can cause a capture condition.
1995 microchip technology inc. ds30390b-page 73 pic16c7x 10.1.1 prescaler there are four prescaler settings, speci?d by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore the ?st capture may be from a non-zero prescaler. example 10-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the ?alse?interrupt. example 10-1: changing between capture prescalers clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new prescaler ; mode value and ccp on movwf ccp1con ;load ccp1con with this ; value 10.1.2 capture mode selection timer1 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. figure 10-2: capture mode operation block diagram 10.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: driven high driven low remains unchanged applicable devices 70 71 71a 72 73 73a 74 74a ccpr1h ccpr1l tmr1h tmr1l set ?g bit ccp1if (pir1<2>) capture enable qs ccp1con<3:0> rc2/ccp1 prescaler ? 1, 4, 16 and edge detect pin the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time, a compare interrupt is also generated. the user must con?ure the rc2/ccp1 pin as an output by clearing the trisc<2> bit. 10.2.1 compare mode selection timer1 must be running in timer mode or synchronized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 10.2.2 software interrupt mode another compare mode is software interrupt mode in which the ccp1 pin is not affected. only a ccp inter- rupt is generated (if enabled). 10.2.3 special event trigger in this mode, an internal hardware trigger is generated which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special trigger output of ccp2 resets the tmr1 register pair, and starts an a/d conversion (if the a/d module is enabled). for the pic16c72 only, the special event trigger output of ccp1 resets the tmr1 register pair, and starts an a/d conversion (if the a/d module is enabled). figure 10-3: compare mode operation block diagram note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the data latch. note: the special event trigger from the ccp1and ccp2 modules will not set inter- rupt ?g bit tmr1if (pir1<0>). ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event (1) trigger set ?g bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin note 1: for ccp1 (if enabled), reset timer1. for ccp2 (if enabled), reset timer1, and set bit go/done (adcon0<2>), which starts an a/d conver- sion.
pic16c7x ds30390b-page 74 1995 microchip technology inc. 10.3 pwm mode in pulse width modulation mode (pwm), pin rc2/ccp1 produces up to a 10-bit resolution pwm output. this pin must be con?ured as an output by clearing the trisc<2> bit. the pin is multiplexed with the data latch. in pwm mode, the user writes the 8-bit duty cycle value to the low byte of the ccpr1 register, namely ccpr1l. the high-byte, ccpr1h is used as the slave buffer to the low byte. the 8-bit data is trans- ferred from the master to the slave when the pwm1 output is set (i.e. at the beginning of the duty cycle). this double buffering is essential for glitchless pwm output. in pwm mode, ccpr1h is readable but not writable. the period of the pwm is determined by the timer2 period register (pr2). pwm period is = [(pr2) + 1] ?4 t osc ?(tmr2 prescale value) pwm duty cycle = (dc1) ?t osc ?(tmr2 prescale value) where dc1 = 10-bit value from ccprxl and ccpx- con<5:4> concatenated. the pwm output resolution is therefore programmable up to a maximum of 10-bits. applicable devices 70 71 71a 72 73 73a 74 74a note: clearing the ccp1con register will force the rc2/ccp1 pwm output latch to the default low level. this is not the i/o data latch. the timer2 postscaler is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. figure 10-4: simplified pwm block diagram table 10-3: pwm frequency vs. resolution at 20 mhz max. resolution frequency (high resolution mode) tmr2 prescale=1 tmr2 prescale=4 tmr2 prescale=16 10-bit 19.53 khz 4.88 khz 1.22 khz 9-bit 39.06 khz 9.77 khz 2.44 khz 8-bit 78.13 khz 19.53 khz 4.88 khz ccprxl ccprxh (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccpxcon<5:4> clear timer, ccp1 pin and latch duty cycle trisc rcy/ccpx pin note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2-bits of the prescaler to create 10-bit time-base. table 10-4: example pwm frequencies and resolutions at 20 mhz pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescaler (16, 4, 1) 16 4 1111 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 resolution (high-resolution mode) 10-bit 10-bit 10-bit 8-bit 7-bit 5.5-bit resolution (standard-resolution mode) (1) 8-bit 8-bit 8-bit 6-bit 5-bit 3.5-bit note 1: standard resolution mode has the ccpxx:ccpxy bits constant (or ??, and only compares the tmr2 register value against the pr2 register value. the q-cycles are not used.
1995 microchip technology inc. ds30390b-page 75 pic16c7x table 10-5: registers associated with capture and timer1 table 10-6: registers associated with compare and timer1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1,2) adif rcif (2) txif (2) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh (2) pir2 ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1,2) adie rcie (2) txie (2) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh (2) pie2 ccp2ie ---- ---0 ---- ---0 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh (2) ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch (2) ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh (2) ccp2con ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by capture and timer1. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. 2: the pic16c72 does not have a parallel slave port, usart or ccp2 module, these bits are unimplemented, read as '0'. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1,2) adif rcif (2) txif (2) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh (2) pir2 ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1,2) adie rcie (2) txie (2) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh (2) pie2 ccp2ie ---- ---0 ---- ---0 0eh tmr1l holding register for the least signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most signi?ant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh (2) ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch (2) ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh (2) ccp2con ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by compare and timer1. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. 2: the pic16c72 does not have a parallel slave port, usart or ccp2 module, these bits are unimplemented, read as '0'.
pic16c7x ds30390b-page 76 1995 microchip technology inc. table 10-7: registers associated with pwm and timer2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1,2) adif rcif (2) txif (2) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh (2) pir2 ccp2if ---- ---0 ---- ---0 8ch pie1 pspie (1,2) adie rcie (2) txie (2) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh (2) pie2 ccp2ie ---- ---0 ---- ---0 11h tmr2 timer2 modules register 0000 0000 0000 0000 92h pr2 timer2 modules period register 1111 1111 1111 1111 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 1bh (2) ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch (2) ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh (2) ccp2con ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by pwm and timer2. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. 2: the pic16c72 does not have a parallel slave port, usart or ccp2 module, these bits are unimplemented, read as '0'.
1995 microchip technology inc. ds30390b-page 77 pic16c7x 11.0 synchronous serial port (ssp) module the synchronous serial port (ssp) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the ssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) applicable devices 70 71 71a 72 73 73a 74 74a refer to application note an578, "use of the ssp mod- ule in the i 2 c multi-master environment." figure 11-1: sspstat: sync serial port status register (address 94h) u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 d/a p s r/w ua bf r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5: d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4: p : stop bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3: s : start bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, sspen is cleared) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2: r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid during the transmission. 1 = read 0 = write bit 1: ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0: bf : buffer full status bit receive (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty t ransmit (i 2 c mode only) 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty this document was created with framemake r404
pic16c7x ds30390b-page 78 1995 microchip technology inc. figure 11-2: sspcon: sync serial port control register (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: wcol : write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6: sspov : receive over?w indicator bit in spi mode 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of over?w, the data in sspsr is lost. over?w can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting over?w. in master mode the over?w bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no over?w in i 2 c mode 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "don? care" in transmit mode. sspov must be cleared in software in either mode. 0 = no over?w bit 5: sspen : synchronous serial port enable bit in spi mode 1 = enables serial port and con?ures sdk, sdo, and sdi as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in i 2 c mode 1 = enables the serial port and con?ures the sda and scl pins as serial port pins 0 = disables serial port and con?ures these pins as i/o port pins in both modes, when enabled, these pins must be properly con?ured as input or output. bit 4: ckp : clock polarity select bit in spi mode 1 = transmit happens on falling edge, receive on rising edge. idle state for clock is a high level 0 = transmit happens on rising edge, receive on falling edge. idle state for clock is a low level in i 2 c mode sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time) bit 3-0: sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. s s pin control enabled. 0101 = spi slave mode, clock = sck pin. s s pin control disabled. s s can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1011 = i 2 c start and stop bit interrupts enabled (slave idle) 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled
1995 microchip technology inc. ds30390b-page 79 pic16c7x 11.1 spi mode the spi mode allows 8-bits of data to be synchro- nously transmitted and received simultaneously. to accomplish communication, typically three pins are used: serial data out (sdo) rc5/sdo serial data in (sdi) rc4/sdi serial clock (sck) rc3/sck additionally a fourth pin may be used when in a slave mode of operation: slave select (ss ) ra5/an4/ss when initializing the spi, several options need to be speci?d. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>). these control bits allow the following to be speci?d: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (output/input data on the rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) the ssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb ?st. the sspbuf holds the data that was previously written to the sspsr, until the received data is ready. once the 8-bits of data have been received, that information is moved to the sspbuf register. then the buffer full detect bit bf (sspstat <0>) and interrupt ?g bit sspif (pir1<3>) are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was received. any write to the sspbuf register during transmission/ reception of data will be ignored, and the write collision detect bit wcol (sspcon<7>) will be set. user soft- ware must clear the wcol bit so that it can be deter- mined if the following write(s) to the sspbuf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit bf (sspstat<0>) indi- cates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, bit bf is cleared. this data may be irrelevant if the spi is only a transmitter. generally the ssp interrupt is used to determine when the transmis- sion/reception has completed. the sspbuf can then be read (if data is meaningful) and/or the sspbuf (sspsr) can be written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 11-1 shows the loading of the sspbuf (sspsr) for data transmission. the shaded instruction is only required if the received data is meaningful. applicable devices 70 71 71a 72 73 73a 74 74a example 11-1: loading the sspbuf (sspsr) register bsf status, rp0 ;specify bank 1 loop btfss sspstat, bf ;has data been ;received ;(transmit ;complete)? goto loop ;no bcf status, rp0 ;specify bank 0 movf sspbuf, w ;w reg = contents ; of sspbuf movf txdata, w ;w reg = contents ; of txdata movwf sspbuf ;new data to xmit the block diagram of the ssp module, when in spi mode (figure 11-3), shows that the sspsr is not directly readable or writable, and can only be accessed from addressing the sspbuf register. additionally, the ssp status register (sspstat) indicates the various status conditions. figure 11-3: ssp block diagram (spi mode) movwf rxdata ;save in user ram read write internal data bus sdi sdo ss sck sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 data from tx/rx in sspsr trisc<3> 2 edge select 2 4
pic16c7x ds30390b-page 80 1995 microchip technology inc. to enable the serial port, ssp enable bit sspen (ssp- con<5>) must be set. to reset or recon?ure spi mode, clear bit sspen, re-initialize the sspcon reg- ister, and then set bit sspen. this con?ures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the trisc register) appro- priately programmed. that is: sdi must have trisc<4> set sdo must have trisc<5> cleared sck (master mode) must have trisc<3> cleared sck (slave mode) must have trisc<3> set ? s must have trisa<5> set any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (tris) register to the opposite value. an example would be in master mode where you are only sending data (to a display driver), then both sdi and ss could be used as general purpose outputs by clearing their corresponding tris register bits. figure 11-4 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their pro- grammed clock edge, and latched on the opposite edge of the clock. both processors should be pro- grammed to same clock polarity (ckp), then both con- trollers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: master sends data slave sends dummy data master sends data slave sends data master sends dummy data slave sends data the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2) wishes to broadcast data by the software protocol. in master mode the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sck output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?ine activity monitor?mode. in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched the interrupt ?g bit sspif (pir1<3>) is set. the clock polarity is selected by appropriately pro- gramming bit ckp (sspcon<4>). this then would give waveforms for spi communication as shown in figure 11-5 and figure 11-6 where the msb is trans- mitted ?st. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ? osc /4 (or t cy ) ? osc /16 (or 4 ?t cy ) ? osc /64 (or 16 ?t cy ) timer2 output/2 this allows a maximum bit clock frequency (at 20 mhz) of 5 mhz. when in slave mode the external clock must meet the minimum high and low times. in sleep mode, the slave can transmit and receive data and wake the device from sleep. figure 11-4: spi master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master (sspm3:sspm0 = 00xxb) serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave (sspm3:sspm0 = 010xb ) serial clock
1995 microchip technology inc. ds30390b-page 81 pic16c7x the ss pin allows a synchronous slave mode. the spi must be in slave mode (sspcon<3:0> = 04h) and the trisa<5> bit must be set the for the synchronous slave mode to be enabled. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmit- ted byte, and becomes a ?ating output. external pull- up/pull-down resistors may be desirable, depending on the application. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver the sdo pin can be con?ured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus con?ct. figure 11-5: spi mode timing (master mode or slave mode w/o ss control) figure 11-6: spi mode timing (slave mode with ss control) sck (ckp = 0) sck (ckp = 1) sdo sdi sspif interrupt ?g bit7 bit7 bit0 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 0) sck (ckp = 1) sdo sdi sspif bit7 bit7 bit0 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ss
pic16c7x ds30390b-page 82 1995 microchip technology inc. table 11-1: registers associated with spi operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1,2) adif rcif (2) txif (2) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1,2) adie rcie (2) txie (2) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 85h trisa trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 94h sspstat d/a p s r/w ua bf --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in spi mode. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. 2: the pic16c72 does not have a parallel slave port or usart, these bits are unimplemented, read as '0'.
1995 microchip technology inc. ds30390b-page 83 pic16c7x 11.2 i 2 c ? over vie w this section provides an overview of the inter-inte- grated circuit (i 2 c) bus, with section 11.3 discussing the operation of the ssp module in i 2 c mode. the i 2 c bus is a two-wire serial interface developed by the philips corporation. the original speci?ation, or standard mode, was for data transfers of up to 100 kbps. an enhanced speci?ation, or fast mode, sup- ports data transmission up to 400 kbps. both standard mode and fast mode devices will inter-operate if attached to the same bus. the i 2 c interface employs a comprehensive protocol to ensure reliable transmission and reception of data. when transmitting data, one device is the ?aster (generates the clock), while the other device(s) acts as the ?lave.?all portions of the slave protocol are imple- mented in the ssp modules hardware, while portions of the master protocol need to be addressed in the pic16cxx software. table 11-2 de?es some of the i 2 c bus terminology. for additional information on the i 2 c interface speci?ation, refer to the philips docu- ment ?he i 2 c bus and how to use it. , which can be obtained from the philips corporation. in the i 2 c interface protocol each device has an address. when a master wishes to initiate a data trans- fer, it ?st transmits the address of the device that it wishes to ?alk?to. all devices ?isten?to see if this is their address. within this address, a bit speci?s if the master wishes to read-from/write-to the slave device. the master and slave are always in opposite modes (transmitter/receiver) of operation during a data trans- fer. that is they can be thought of operating in either of these two relations: master-transmitter and slave-receiver slave-transmitter and master-receiver in both cases the master generates the clock signal. applicable devices 70 71 71a 72 73 73a 74 74a the output stages of the clock (scl) and data (sda) lines must have an open-drain or open-collector in order to perform the wired-and function of the bus. external pull-up resistors are used to ensure a high level when no device is pulling the line down. the num- ber of devices that may be attached to the i 2 c bus is limited only by the maximum bus loading speci?ation of 400 pf. 11.2.1 initiating and terminating data transfer during times of no data transfer (idle time), both the clock line (scl) and the data line (sda) are pulled high through the external pull-up resistors. the start and stop conditions determine the start and stop of data transmission. the start condition is de?ed as a high to low transition of the sda when the scl is high. the stop condition is de?ed as a low to high transition of the sda when the scl is high. figure 11-7 shows the start and stop conditions. the master generates these conditions for starting and terminating data trans- fer. due to the de?ition of the start and stop con- ditions, when data is being transmitted, the sda line can only change state when the scl line is low. figure 11-7: start and stop conditions sda scl s p start condition change of data allowed change of data allowed stop condition table 11-2: i 2 c bus terminology term description transmitter the device that sends the data to the bus. receiver the device that receives the data from the bus. master the device which initiates the transfer, generates the clock and terminates the transfer. slave the device addressed by a master. multi-master more than one master device in a system. these masters can attempt to control the bus at the same time without corrupting the message. arbitration procedure that ensures that only one of the master devices will control the bus. this ensure that the transfer data does not get corrupted. synchronization procedure where the clock signals of two or more devices are synchronized.
pic16c7x ds30390b-page 84 1995 microchip technology inc. 11.2.2 addressing i 2 c devices there are two address formats. the simplest is the 7-bit address format with a r/w bit (figure 11-8). the more complex is the 10-bit address with a r/w bit (figure 11-9). for 10-bit address format, two bytes must be transmitted with the ?st ?e bits specifying this to be a 10-bit address. figure 11-8: 7-bit address format figure 11-9: i 2 c 10-bit address format s r/w ack sent by slave slave address s r/w read/write pulse msb lsb start condition ack acknowledge s 1 1 1 1 0 a9 a8 r/w ack a7 a6 a5 a4 a3 a2 a1 a0 ack sent by slave = 0 for write s r/w ack - start condition - read/write pulse - acknowledge 11.2.3 transfer acknowledge all data must be transmitted per byte, with no limit to the number of bytes transmitted per data transfer. after each byte, the slave-receiver generates an acknowl- edge bit (ack ) (figure 11-10). when a slave-receiver doesn? acknowledge the slave address or received data, the master must abort the transfer. the slave must leave sda high so that the master can generate the stop condition (figure 11-7). figure 11-10: slave-receiver acknowledge if the master is receiving the data (master-receiver), it generates an acknowledge signal for each received byte of data, except for the last byte. to signal the end of data to the slave-transmitter, the master does not generate an acknowledge (not acknowledge). the slave then releases the sda line so the master can generate the stop condition. the master can also generate the stop condition during the acknowledge pulse for valid termination of data transfer. if the slave needs to delay the transmission of the next byte, holding the scl line low will force the master into a wait state. data transfer continues when the slave releases the scl line. this allows the slave to move the received data or fetch the data it needs to transfer before allowing the clock to start. this wait state tech- nique can also be implemented at the bit level, figure 11-11. s data output by transmitter data output by receiver scl from master start condition clock pulse for acknowledgment not acknowledge acknowledge 1 2 8 9 figure 11-11: data transfer wait state 12 78 9 123 89 p sda scl s start condition address r/w ack wait state data ack msb acknowledgment signal from receiver acknowledgment signal from receiver byte complete interrupt with receiver clock line held low while interrupts are serviced stop condition
1995 microchip technology inc. ds30390b-page 85 pic16c7x figure 11-12 and figure 11-13 show master-transmit- ter and master-receiver data transfer sequences. when a master does not wish to relinquish the bus (by generating a stop condition), a repeated start con- dition (sr) must be generated. this condition is identi- cal to the start condition (sda goes high-to-low while scl is high), but occurs after a data transfer acknowl- edge pulse (not the bus-free state). this allows a mas- ter to send ?ommands?to the slave and then receive the requested information or to address a different slave device. this sequence is shown in figure 11-14. figure 11-12: master-transmitter sequence figure 11-13: master-receiver sequence figure 11-14: combined format for 7-bit address: s slave address first 7 bits s r/w a1 slave address second byte a2 data a data p a master transmitter addresses a slave receiver with a 10-bit address. a/a slave address r/w a data a data a/a p '0' (write) data transferred (n bytes - acknowledge) a master transmitter addresses a slave receiver with a 7-bit address. the transfer direction is not changed. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition (write) for 10-bit address: for 7-bit address: s slave address first 7 bits s r/w a1 slave address second byte a2 a master transmitter addresses a slave receiver with a 10-bit address. slave address r/w a data a data a p '1' (read) data transferred (n bytes - acknowledge) a master reads a slave immediately after the ?st byte. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition (write) for 10-bit address: slave address first 7 bits sr r/w a3 a data a p data (read) combined format: s combined format - a master addresses a slave with a 10-bit address, then transmits slave address r/w a data a/a sr p (read) sr = repeated transfer direction of data and acknowledgment bits depends on r/w bits. from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition slave address first 7 bits sr r/w a (write) data to this slave and reads data from this slave. slave address second byte data sr slave address first 7 bits r/w a data a a p a a data a/a data (read) slave address r/w a data a/a start condition (write) direction of transfer may change at this point (read or write) (n bytes + acknowledge)
pic16c7x ds30390b-page 86 1995 microchip technology inc. 11.2.4 multi-master the i 2 c protocol allows a system to have more than one master. this is called multi-master. when two or more masters try to transfer data at the same time, arbi- tration and synchronization occur. 11.2.4.1 arbitration arbitration takes place on the sda line, while the scl line is high. the master which transmits a high when the other master transmits a low loses arbitration (figure 11-15), and turns off its data output stage. a master which lost arbitration can generate clock pulses until the end of the data byte where it lost arbitration. when the master devices are addressing the same device, arbitration continues into the data. figure 11-15: multi-master arbitration (two masters) masters that also incorporate the slave function, and have lost arbitration must immediately switch over to slave-receiver mode. this is because the winning mas- ter-transmitter may be addressing it. arbitration is not allowed between: a repeated start condition a stop condition and a data bit a repeated start condition and a stop condi- tion care needs to be taken to ensure that these conditions do not occur. transmitter 1 loses arbitration data 1 sda data 1 data 2 sda scl 11.2.4.2 clock synchronization clock synchronization occurs after the devices have started arbitration. this is performed using a wired- and connection to the scl line. a high to low transition on the scl line causes the concerned devices to start counting off their low period. once a device clock has gone low, it will hold the scl line low until its scl high state is reached. the low to high transition of this clock may not change the state of the scl line, if another device clock is still within its low period. the scl line is held low by the device with the longest low period. devices with shorter low periods enter a high wait- state, until the scl line comes high. when the scl line comes high, all devices start counting off their high periods. the ?st device to complete its high period will pull the scl line low. the scl line high time is deter- mined by the device with the shortest high period, figure 11-16. figure 11-16: clock synchronization clk 1 clk 2 scl wait state start counting high period counter reset
1995 microchip technology inc. ds30390b-page 87 pic16c7x 11.3 ssp i 2 c operation the ssp module in i 2 c mode fully implements all slave functions, and provides interrupts on start and stop bits in hardware to facilitate software implementations of the master functions. the ssp module implements the standard and fast mode speci?ations as well as 7-bit and 10-bit addressing. two pins are used for data transfer. these are the rc3/sck/scl pin, which is the clock (scl), and the rc4/sdi/sda pin, which is the data (sda). the user must con?ure these pins as inputs or outputs through the trisc<4:3> bits. the ssp module functions are enabled by setting ssp enable bit sspen (sspcon<5>). figure 11-17: ssp block diagram (i 2 c mode) the ssp module has ?e registers for i 2 c operation. these are the: ssp control register (sspcon) ssp status register (sspstat) serial receive/transmit buffer (sspbuf) ssp shift register (sspsr) - not directly acces- sible ssp address register (sspadd) applicable devices 70 71 71a 72 73 73a 74 74a read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ? 2 c slave mode (7-bit address) ? 2 c slave mode (10-bit address) ? 2 c slave mode (7-bit address), with start and stop bit interrupts enabled ? 2 c slave mode (10-bit address), with start and stop bit interrupts enabled ? 2 c start and stop bit interrupts enabled, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. the sspstat register gives the status of the data transfer. this information includes detection of a start or stop bit, speci?s if the received byte was data or address if the next byte is the completion of 10- bit address, and if this will be a read or write data trans- fer. the sspstat register is read only. the sspbuf is the register to which transfer data is written to or read from. the sspsr register shifts the data in or out of the device. in receive operations, the sspbuf and sspsr create a doubled buffered receiver. this allows reception of the next byte to begin before reading the last byte of received data. when the complete byte is received, it is transferred to the ssp- buf register and ?g bit sspif is set. if another com- plete byte is received before the sspbuf register is read, a receiver over?w has occurred and bit sspov (sspcon<6>) is set. the sspadd register holds the slave address. in 10-bit mode, the user needs to write the high byte of the address ( 1111 0 a9 a8 0 ). following the high byte address match, the low byte of the address needs to be loaded (a7:a0).
pic16c7x ds30390b-page 88 1995 microchip technology inc. 11.3.1 slave mode in slave mode, the scl and sda pins must be con?- ured as inputs (trisc<4:3> set). the ssp module will override the input state with the output data when required (slave-transmitter). when an address is matched or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse, and then load the sspbuf register with the received value currently in the sspsr register. there are certain conditions that will cause the ssp module not to give this ack pulse. these are if either (or both): a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the over?w bit sspov (sspcon<6>) was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. table 11-3 shows what happens when a data transfer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user software did not properly clear the over?w condi- tion. flag bit bf is cleared by reading the sspbuf reg- ister while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c speci?ation as well as the requirement of the ssp module is shown in timing parameter #100 and param- eter #101. 11.3.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condi- tion, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit, bf is set. c) an ack pulse is generated. d) ssp interrupt ?g bit, sspif (pir1<3>) is set (interrupt is generated if enabled) - on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave (figure 11-9). the ?e most sig- ni?ant bits (msbs) of the ?st address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write, so the slave device will receive the sec- ond address byte. for a 10-bit address the ?st byte would equal 1111 0 a9 a8 0 ? where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit address are as follows, with steps 7- 9 for slave-transmitter: 1. receive ?st (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear ?g bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the ?st (high) byte of address (clears bit ua, if match releases scl line). 6. read the sspbuf register (clears bit bf) and clear ?g bit sspif. 7. receive repeated start condition. 8. receive ?st (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear ?g bit sspif. table 11-3: data transfer received byte actions status bits as data transfer is received sspsr ? sspbuf generate a ck pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 yes yes yes 10 no no yes 11 no no yes 0 1 no no yes
1995 microchip technology inc. ds30390b-page 89 pic16c7x 11.3.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte over?w condition exists, then no acknowledge (ack ) pulse is given. an over?w con- dition is de?ed as either bit bf (sspstat<0>) is set or bit sspov (sspcon<6>) is set. an ssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware, and the sspstat register is used to determine the status of the byte. figure 11-18: i 2 c waveforms for reception (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w =0 receiving address sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon<6>) ack ack is not sent.
pic16c7x ds30390b-page 90 1995 microchip technology inc. 11.3.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the ssp- stat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit, and pin rc3/sck/scl is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then pin rc3/ sck/scl should be enabled by setting bit ckp (ssp- con<4>). the eight data bits are shifted out on the fall- ing edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 11-19). an ssp interrupt is generated for each data transfer byte. flag bit sspif must be cleared in software, and the sspstat register is used to determine the status of the byte. flag bit sspif is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the a ck pulse from the master- receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not ack ), then the data transfer is complete. the slave then monitors for another occurrence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr reg- ister. then pin rc3/sck/scl should be enabled by setting bit ckp. figure 11-19: i 2 c waveforms for transmission (7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif
1995 microchip technology inc. ds30390b-page 91 pic16c7x 11.3.2 master mode master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is dis- abled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle and both the s and p bits are clear. in master mode the scl and sda lines are manipu- lated by clearing the corresponding trisc<4:3> bit(s). the output level is always low, irrespective of the value(s) in portb<4:3>. so when transmitting data, a '1' data bit must have the trisc<4> bit set (input) and a '0' data bit must have the trisc<4> bit cleared (out- put). the same scenario is true for the scl line with the trisc<3> bit. the following events will cause the ssp interrupt flag bit sspif to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received master mode of operation can be done with either the slave mode idle (sspm3:sspm0 = 1011 ) or with the slave active. when both master and slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. 11.3.3 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle and both the s and p bits are cleared. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored to see if the signal level is the expected output level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set trisc<4:3>). there are two stages where this arbitration can be lost, these are: address transfer data transfer when the slave logic is enabled, the slave continues to receive. if arbitration was lost during the address trans- fer stage, the device may be being addressed. if addressed an ack pulse will be generated. if arbitra- tion was lost during the data transfer stage, the device will need to re-transfer the data at a later time. table 11-4: registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1,2) adif rcif (2) txif (2) sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1,2) adie rcie (2) txie (2) sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat d/a p s r/w ua bf --00 0000 --00 0000 89h trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by ssp in i 2 c mode. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. 2: the pic16c72 does not have a parallel slave port or usart, these bits are unimplemented, read as '0'.
pic16c7x ds30390b-page 92 1995 microchip technology inc. figure 11-20: operation of the i 2 c module in idle_mode, rcv_mode or xmit_mode i dle_mode (7-bit): if (addr_match) { set interrupt; if (r/w = 1) { send a ck = 0; set xmit_mode; } else if (r/w = 0) set rcv_mode; } rcv_mode: if ((sspbuf=full) or (sspov = 1)) { set sspov; do not acknowledge; } else { transfer sspsr ? sspbuf; send ack = 0; } receive 8-bits in sspsr; set interrupt; xmit_mode: while ((sspbuf = empty) and (ckp=0)) hold scl low; send byte; set interrupt; if ( ack received = 1) { end of transmission; go back to idle_mode; } else if ( ack received = 0) go back to xmit_mode; idle_mode (10-bit): if (high_byte_addr_match and (r/w = 0)) { prior_addr_match = false; set interrupt; if ((sspbuf = full) or ((sspov = 1)) { set sspov; do not acknowledge; } else { set ua = 1; send ack = 0; while (sspadd not updated) hold scl low; clear ua = 0; receive low_addr_byte; set interrupt; set ua = 1; if (low_byte_addr_match) { prior_addr_match = true; send ack = 0; while (sspadd not updated) hold scl low; clear ua = 0; set rcv_mode; } } } else if (high_byte_addr_match and (r/w = 1) { if (prior_addr_match) { send ack = 0; set xmit_mode; } else prior_addr_match = false; }
1995 microchip technology inc. ds30390b-page 93 pic16c7x 12.0 universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also know as a serial commu- nications interface or sci). the usart can be con?- ured as a full duplex asynchronous system that can communicate with peripheral devices such as crt ter- minals and personal computers, or it can be con?ured applicable devices 70 71 71a 72 73 73a 74 74a as a half duplex synchronous system that can commu- nicate with peripheral devices such as a/d or d/a inte- grated circuits, serial eeproms etc. the usart can be con?ured in the following modes: asynchronous (full duplex) synchronous - master (half duplex) synchronous - slave (half duplex) bit spen (rcsta<7>), and bits trisc<7:6>, have to be set in order to con?ure pins rc6/tx/ck and rc7/rx/dt for the serial communication interface. figure 12-1: txsta: transmit status and control register (address 98h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync brgh trmt tx9d r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: csrc : clock source select bit asynchronous mode don? care synchronous mode 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6: tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5: txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4: sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3: unimplemented: read as '0' bit 2: brgh : high baud rate select bit asynchronous mode 1 = high speed 0 = low speed synchronous mode unused in this mode bit 1: trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0: tx9d : 9th bit of transmit data. can be parity bit. this document was created with framemake r404
pic16c7x ds30390b-page 94 1995 microchip technology inc. figure 12-2: rcsta: receive status and control register (address 18h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r-0 r-x spen rx9 sren cren ferr oerr rx9d r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: spen : serial port enable bit 1 = serial port enabled (con?ures rc7/rx/dt and rc6/tx/ck pins as serial port pins) 0 = serial port disabled bit 6: rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5: sren : single receive enable bit asynchronous mode don? care synchronous mode - master 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - slave unused in this mode bit 4: cren : continuous receive enable bit asynchronous mode 1 = enables continuous receive 0 = disables continuous receive synchronous mode 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3: unimplemented: read as '0' bit 2: ferr : framing error bit 1 = framing error (can be updated by reading rcreg register) 0 = no framing error bit 1: oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0: rx9d : 9th bit of received data (can be parity bit)
1995 microchip technology inc. ds30390b-page 95 pic16c7x 12.1 u sar t baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode bit brgh (txsta<2>) also controls the baud rate. in synchronous mode bit brgh is ignored. table 12-1 shows the formula for computation of the baud rate for different usart modes which only apply in master mode (internal clock). given the desired baud rate and fosc, the nearest inte- ger value for the spbrg register can be calculated using the formula in table 12-1. from this, the error in baud rate can be determined. example 12-1 shows the calculation of the baud rate error for the following conditions: f osc = 16 mhz desired baud rate = 9600 brgh = 0 sync = 0 applicable devices 70 71 71a 72 73 73a 74 74a example 12-1: calculating baud rate error it may be advantageous to use the high baud rate (brgh = 1) even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register, causes the brg timer to be reset (or cleared), this ensures the brg does not wait for a timer over?w before output- ting the new baud rate. desired baud rate=fosc / (64 (x + 1)) 9600 = 16000000 /(64 (x + 1)) x= ? 25.042 ? = 25 calculated baud rate=16000000 / (64 (25 + 1)) = 9615 error = ( calculated baud rate - desired baud rate) desired baud rate = (9615 - 9600) / 9600 = 0.16% table 12-1: baud rate formula table 12-2: registers associated with baud rate generator sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(x+1)) (synchronous) baud rate = f osc /(4(x+1)) baud rate= f osc /(16(x+1)) na x = value in spbrg (0 to 255) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used by the brg.
pic16c7x ds30390b-page 96 1995 microchip technology inc. table 12-3: baud rates for synchronous mode table 12-4: baud rates for asynchronous mode (brgh = 0) baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) kbaud %error kbaud %error kbaud %error kbaud %error 0.3 na - - na - - na - - na - - 1.2 na - - na - - na - - na - - 2.4 na - - na - - na - - na - - 9.6 na - - na - - 9.766 +1.73 255 9.622 +0.23 185 19.2 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 76.8 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 96 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 300 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 298.3 -0.57 5 500 500 0 9 500 0 7 500 0 4 na - - high 5000 - 0 4000 - 0 2500 - 0 1789.8 - 0 low 19.53 - 255 15.625 - 255 9.766 - 255 6.991 - 255 baud rate (k) f osc = 5.0688 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud %error kbaud %error kbaud %error kbaud %error 0.3 na - - na - - na - - 0.303 +1.14 26 1.2 na - - na - - 1.202 +0.16 207 1.170 -2.48 6 2.4 na - - na - - 2.404 +0.16 103 na - - 9.6 9.6 0 131 9.622 +0.23 92 9.615 +0.16 25 na - - 19.2 19.2 0 65 19.04 -0.83 46 19.24 +0.16 12 na - - 76.8 79.2 +3.13 15 74.57 -2.90 11 83.34 +8.51 2 na - - 96 97.48 +1.54 12 99.43 +3.57 8 na - - na - - 300 316.8 +5.60 3 298.3 -0.57 2 na - - na - - 500 na - - na - - na - - na - - high 1267 - 0 894.9 - 0 250 - 0 8.192 - 0 low 4.950 - 255 3.496 - 255 0.9766 - 255 0.032 - 255 baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) kbaud %error kbaud %error kbaud %error kbaud %error 0.3 na - - na - - na - - na - - 1.2 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 1.203 +0.23 92 2.4 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 2.380 -0.83 46 9.6 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 9.322 -2.90 11 19.2 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 76.8 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 na - - 96 104.2 +8.51 2 na - - na - - na - - 300 312.5 +4.17 0 na - - na - - na - - 500 na - - na - - na - - na - - high 312.5 - 0 250 - 0 156.3 - 0 111.9 - 0 low 1.221 - 255 0.977 - 255 0.6104 - 255 0.437 - 255 baud rate (k) f osc = 5.0688 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud %error kbaud %error kbaud %error kbaud %error 0.3 0.31 +3.13 255 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1 1.2 1.2 0 65 1.190 -0.83 46 1.202 +0.16 12 na - - 2.4 2.4 0 32 2.432 +1.32 22 2.232 -6.99 6 na - - 9.6 9.9 +3.13 7 9.322 -2.90 5 na - - na - - 19.2 19.8 +3.13 3 18.64 -2.90 2 na - - na - - 76.8 79.2 +3.13 0 na - - na - - na - - 96 na - - na - - na - - na - - 300 na - - na - - na - - na - - 500 na - - na - - na - - na - - high 79.2 - 0 55.93 - 0 15.63 - 0 0.512 - 0 low 0.3094 - 255 0.2185 - 255 0.0610 - 255 0.0020 - 255
1995 microchip technology inc. ds30390b-page 97 pic16c7x table 12-5: baud rates for asynchronous mode (brgh = 1) baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.16 mhz spbrg value (decimal) kbaud %error kbaud %error kbaud %error kbaud %error 9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 9.520 -0.83 46 19.2 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 19.454 +1.32 22 38.4 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 37.286 -2.90 11 57.6 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 55.930 -2.90 7 115.2 113.636 -1.36 10 111.111 -3.55 8 125 +8.51 4 111.860 -2.90 3 250 250 0 4 250 0 3 na - - na - - 625 625 0 1 na - - 625 0 0 na - - 1250 1250 0 0 na - - na - - na - - baud rate (k) f osc = 5.068 mhz spbrg value (decimal) 3.579 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud %error kbaud %error kbaud %error kbaud %error 9.6 9.6 0 32 9.727 +1.32 22 8.928 -6.99 6 na - - 19.2 18.645 -2.94 16 18.643 -2.90 11 20.833 +8.51 2 na - - 38.4 39.6 +3.12 7 37.286 -2.90 5 31.25 -18.61 1 na - - 57.6 52.8 -8.33 5 55.930 -2.90 3 62.5 +8.51 0 na - - 115.2 105.6 -8.33 2 111.860 -2.90 1 na - - na - - 250 na - - 223.721 -10.51 0 na - - na - - 625 na - - na - - na - - na - - 1250 na - - na - - na - - na - -
pic16c7x ds30390b-page 98 1995 microchip technology inc. 12.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. if bit brgh (txsta<2>) is clear (i.e., at the low baud rates), the sampling is done on the seventh, eighth and ninth fall- ing edges of a x16 clock (figure 12-3). if bit brgh is set (i.e., at the high baud rates), the sampling is done on the 3 clock edges preceding the second rising edge after the ?st falling edge of a x4 clock (figure 12-4 and figure 12-5). figure 12-3: rx pin sampling scheme (brgh = 0) figure 12-4: rx pin sampling scheme (brgh = 1) figure 12-5: rx pin sampling scheme (brgh = 1) rx baud clk x16 clk start bit bit0 samples 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 baud clk for all but start bit (rc7/rx/dt pin) rx pin baud clk x4 clk q2, q4 clk start bit bit0 bit1 first falling edge after rx pin goes low second rising edge samples samples samples 1234123412 rx pin baud clk x4 clk q2, q4 clk start bit bit0 first falling edge after rx pin goes low second rising edge samples 12 3 4 baud clk for all but start bit
1995 microchip technology inc. ds30390b-page 99 pic16c7x 12.2 usar t a sync hr onous mode in this mode, the usart uses standard nonreturn-to- zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8-bits. an on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the usart transmits and receives the lsb first. the usarts transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing bit sync (txsta<4>). the usart asynchronous module consists of the fol- lowing important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 12.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 12-6. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and applicable devices 70 71 71a 72 73 73a 74 74a ?g bit txif (pir1<4>) is set. this interrupt can be enabled or disabled by setting/clearing enable bit txie ( pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while ?g bit txif indicated the sta- tus of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. sta- tus bit trmt is a read only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data and the baud rate generator (brg) has produced a shift clock (figure 12-6). the transmission can also be started by ?st loading the txreg register and then setting enable bit txen. normally when transmission is ?st started, the tsr register is empty, so a transfer to the txreg register will result in an immediate trans- fer to tsr resulting in an empty txreg. a back-to- back transfer is thus possible (figure 12-8). clearing enable bit txen during a transmission will cause the transmission to be aborted and will reset the transmit- ter. as a result the rc6/tx/ck pin will revert to hi- impedance. in order to select 9-bit transmission, transmit bit tx9 (txsta<6>) should be set and the ninth bit should be written to tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg reg- ister. this is because a data write to the txreg regis- ter can result in an immediate transfer of the data to the tsr register (if the tsr is empty). in such a case, an incorrect ninth data bit maybe loaded in the tsr regis- ter. note 1: the tsr register is not mapped in data memory so it is not available to the user. note 2: flag bit txif is set when enable bit txen is set. figure 12-6: usart transmit block diagram txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8
pic16c7x ds30390b-page 100 1995 microchip technology inc. steps to follow when setting up a asynchronous trans- mission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. (section 12.1) 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set transmit bit tx9. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts trans- mission). figure 12-7: asynchronous master transmission figure 12-8: asynchronous master transmission (back to back) table 12-6: registers associated with asynchronous transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous transmission. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty ?g) trmt bit (transmit shift reg. empty ?g) transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. ?g) trmt bit (transmit shift reg. empty ?g) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions.
1995 microchip technology inc. ds30390b-page 101 pic16c7x 12.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 12-9. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter oper- ates at the bit rate or at f osc . once asynchronous mode is selected, reception is enabled by setting bit cren (rcsta<4>). the heart of the receiver is the receive (serial) shift reg- ister (rsr). after sampling the stop bit, the received data in the rsr is transferred to the rcreg register (if it is empty). if the transfer is complete, ?g bit rcif (pir1<5>) is set. the actual interrupt can be enabled or disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read only bit which is reset by the hardware. it is cleared when the rcreg register has been read and is empty. the rcreg is a double buffered register, i.e. it is a two deep fifo. it is possible for two bytes of data to be received and trans- ferred to the rcreg fifo and a third byte begin shift- ing to the rsr register. on the detection of the stop bit of the third byte, if the rcreg register is still full then overrun error bit oerr (rcsta<1>) will be set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. overrun bit oerr has to be cleared in software. this is done by resetting the receive logic (cren is cleared and then set). if bit oerr is set, transfers from the rsr register to the rcreg register are inhibited, so it is essential to clear error bit oerr if it is set. framing error bit ferr (rcsta<2>) is set if a stop bit is detected as clear. bit ferr and the 9th receive bit are buffered the same way as the receive data. reading the rcreg, will load bits rx9d and ferr with new values, therefore it is essential for the user to read the rcsta register before reading rcreg register in order not to lose the old ferr and rx9d information. figure 12-9: usart receive block diagram figure 12-10: asynchronous reception x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 ? 64 ? 16 or stop start (8) 7 1 0 rx9 start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt ?g) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set.
pic16c7x ds30390b-page 102 1995 microchip technology inc. steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. (section 12.1). 2. enable the asynchronous serial port by clearing bit sync, and setting bit spen. 3. if interrupts are desired, then set enable bit rcie. 4. if 9-bit reception is desired, then set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie were set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. table 12-7: registers associated with asynchronous reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous reception. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear.
1995 microchip technology inc. ds30390b-page 103 pic16c7x 12.3 usar t s ync h r onous master mode in master synchronous mode, the data is transmitted in a half-duplex manner i.e. transmission and reception do not occur at the same time. when transmitting data, the reception is inhibited and vice versa. the synchro- nous mode is entered by setting bit sync (txsta<4>). in addition enable bit spen (rcsta<7>) is set in order to con?ure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines respectively. the master mode indicates that the pro- cessor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta<7>). 12.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 12-6. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one tcycle), the txreg is empty and an interrupt bit, txif (pir1<4>) is set. the interrupt can be enabled or disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while ?g bit txif indicates the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. trmt is a read only bit which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr reg- ister is empty. the tsr is not mapped in data memory so it is not available to the user. transmission is enabled by setting enable bit txen (txsta<5>). the actual transmission will not occur until the txreg register has been loaded with data. the ?st data bit will be shifted out on the next available rising edge of the clock on the ck line. data out is sta- ble around the falling edge of the synchronous clock (figure 12-11). the transmission can also be started by ?st loading the txreg register and then setting bit txen. this is advantageous when slow baud rates are selected, since the brg is kept in reset when bits txen, cren, and sren are clear. setting enable bit txen will start the brg, creating a shift clock immedi- ately. normally when transmission is ?st started, the tsr register is empty, so a transfer to the txreg reg- ister will result in an immediate transfer to tsr result- ing in an empty txreg. back-to-back transfers are possible. applicable devices 70 71 71a 72 73 73a 74 74a clearing enable bit txen, during a transmission, will cause the transmission to be aborted and will reset the transmitter. the dt and ck pins will revert to hi-imped- ance. if either bit cren or bit sren are set, during a transmission, the transmission is aborted and the dt pin reverts to a hi-impedance state (for a reception). the ck pin will remain an output if bit csrc is set (internal clock). the transmitter logic however is not reset although it is disconnected from the pins. in order to reset the transmitter, the user has to clear bit txen. if bit sren is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit sren will be cleared and the serial port will revert back to transmitting since bit txen is still set. the dt line will immediately switch from hi-impedance receive mode to transmit and start driving. to avoid this, bit txen should be cleared. in order to select 9-bit transmission, the tx9 (txsta<6>) bit should be set and the ninth bit should be written to bit tx9d (txsta<0>). the ninth bit must be written before writing the 8-bit data to the txreg register. this is because a data write to the txreg can result in an immediate transfer of the data to the tsr register (if the tsr is empty). if the tsr was empty and the txreg was written before writing the ?ew?tx9d, the ?resent?value of bit tx9d is loaded. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (section 12.1). 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register.
pic16c7x ds30390b-page 104 1995 microchip technology inc. table 12-8: registers associated with synchronous master transmission figure 12-11: synchronous transmission figure 12-12: synchronous transmission (through txen) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master transmission. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. bit 0 bit 1 bit 7 word 1 q1q2 q3q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2 q3q4 q3q4 q1q2 q3q4 q1q2 q3q4 q1q2 q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit (interrupt flag) trmt txen bit '1' '1' note: sync master mode; spbrg = '0'. continuous transmission of two 8-bit words word 2 trmt bit write word1 write word2 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit0 bit1 bit2 bit6 bit7
1995 microchip technology inc. ds30390b-page 105 pic16c7x 12.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit sren (rcsta<5>) or enable bit cren (rcsta<4>). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, then only a single word is received. if enable bit cren is set, the recep- tion is continuous until cren is cleared. if both bits are set then cren takes precedence. after clocking the last bit, the received data in the receive shift register (rsr) is transferred to the rcreg register (if it is empty). when the transfer is complete, interrupt ?g bit rcif (pir1<5>) is set. the actual interrupt can be enabled/disabled by setting/clearing enable bit rcie (pie1<5>). flag bit rcif is a read only bit which is reset by the hardware. in this case it is reset when the rcreg register has been read and is empty. the rcreg is a double buffered register, i.e. it is a two deep fifo. it is possible for two bytes of data to be received and transferred to the rcreg fifo and a third byte to begin shifting into the rsr register. on the clocking of the last bit of the third byte, if the rcreg register is still full then overrun error bit oerr (rcsta<1>) is set. the word in the rsr will be lost. the rcreg register can be read twice to retrieve the two bytes in the fifo. bit oerr has to be cleared in software (by clearing bit cren). if bit oerr is set, transfers from the rsr to the rcreg are inhibited, so it is essential to clear bit oerr if it is set. the 9th receive bit is buffered the same way as the receive data. reading the rcreg register, will load bit rx9d with a new value, therefore it is essential for the user to read the rcsta register before reading rcreg in order not to lose the old rx9d information. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate. (section 12.1) 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, then set enable bit rcie. 5. if 9-bit reception is desired, then set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception set bit cren. 7. interrupt ?g bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. table 12-9: registers associated with synchronous master reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous master reception. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear.
pic16c7x ds30390b-page 106 1995 microchip technology inc. figure 12-13: synchronous reception (master mode, sren) cren bit dt pin ck pin write to sren bit sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with sren = '1' and brg = '0'. q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 '0' q1 q2 q3 q4
1995 microchip technology inc. ds30390b-page 107 pic16c7x 12.4 usar t s ync hr onous sla ve mode synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in the master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta<7>). 12.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the ?st word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the ?st word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and ?g bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep and if the global interrupt is enabled, the program will branch to the inter- rupt vector (0004h). steps to follow when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. applicable devices 70 71 71a 72 73 73a 74 74a 12.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of the sleep mode. also, bit sren is a don't care in slave mode. if receive is enabled, by setting bit cren, prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, then set enable bit rcie. 3. if 9-bit reception is desired, then set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete and an interrupt will be generated, if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren.
pic16c7x ds30390b-page 108 1995 microchip technology inc. table 12-10: registers associated with synchronous slave transmission table 12-11: registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 19h txreg tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave transmission. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren ferr oerr rx9d 0000 -00x 0000 -00x 1ah rcreg rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave reception. note 1: bits pspie and pspif are reserved on the pic16c73/73a, always maintain these bits clear.
1995 microchip technology inc. ds30390b-page 109 pic16c7x figure 13-1: adcon0 register, PIC16C70/71/71a (address 08h) r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs1 adcs0 (1) chs1 chs0 go/done adif adon r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7-6: adcs1:adcs0: a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from an rc oscillation) bit 5: unimplemented : read as '0'. bit 4-3: chs2:chs0 : analog channel select bits 00 = channel 0, (ra0/an0) 01 = channel 1, (ra1/an1) 10 = channel 2, (ra2/an2) 11 = channel 3, (ra3/an3) bit 2: go/done : a/d conversion status bit if adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conver- sion is complete) bit 1: adif: a/d conversion complete interrupt flag bit 1 = conversion is complete (must be cleared in software) 0 = conversion is not complete bit 0: adon: a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current note 1: bit5 of adcon0 is a general purpose r/w bit for the pic16c71 only. for the PIC16C70/71a, this bit is unimplemented, read as '0'. 13.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has four analog inputs for the PIC16C70/71/71a, ?e inputs for the pic16c72/73/73a, and eight for the pic16c74/74a. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to applica- tion note an546 for use of a/d converter). the output of the sample and hold is the input into the converter, which generates the result via successive approxima- tion. the analog reference voltage is software select- able to either the devices positive supply voltage (v dd ) applicable devices 70 71 71a 72 73 73a 74 74a or the voltage level on the ra3/an3/v ref pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. the a/d module has three registers. these registers are: a/d result register (adres) a/d control register 0 (adcon0) a/d control register 1 (adcon1) the adcon0 register, shown in figure 13-1 and figure 13-2, controls the operation of the a/d module. the adcon1 register, shown in figure 13-3 and figure 13-4, con?ures the functions of the port pins. the port pins can be con?ured as analog inputs (ra3 can also be a voltage reference) or as digital i/o. this document was created with framemake r404
pic16c7x ds30390b-page 110 1995 microchip technology inc. figure 13-2: adcon0 register, pic16c72/73/73a/74/74a (address 1fh) figure 13-3: adcon1 register for PIC16C70/71/71a (address 88h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done adon r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-6: adcs1:adcs0: a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from an rc oscillation) bit 5-3: chs2:chs0 : analog channel select bits 000 = channel 0, (ra0/an0) 001 = channel 1, (ra1/an1) 010 = channel 2, (ra2/an2) 011 = channel 3, (ra3/an3) 100 = channel 4, (ra5/an4) 101 = channel 5, (re0/an5) 110 = channel 6, (re1/an6) 111 = channel 7, (re2/an7) bit 2: go/done : a/d conversion status bit if adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1: unimplemented : read as '0' bit 0: adon : a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 pcfg1 pcfg0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1-0: pcfg1:pcfg0 : a/d port con?uration control bits a = analog input d = digital i/o pcfg1:pcfg0 ra1 & ra0 ra2 ra3 v ref 00 a aav dd 01 aav ref ra3 10 a ddv dd 11 d ddv dd
1995 microchip technology inc. ds30390b-page 111 pic16c7x figure 13-4: adcon1 register, pic16c72/73/73a/74/74a (address 9fh) u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 pcfg2 pcfg1 pcfg0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7-3: unimplemented: read as '0' bit 2-0: pcfg2:pcfg0 : a/d port con?uration control bits a = analog input d = digital i/o pcfg2:pcfg0 ra0 ra1 ra2 ra5 ra3 re0 re1 re2 v ref 000 aaaaa aaav dd 001 aaaav ref aaara3 010 aaaaa dddv dd 011 aaaav ref dddra3 100 aadda dddv dd 101 aaddv ref dddra3 11x ddddd ddd
pic16c7x ds30390b-page 112 1995 microchip technology inc. the adres register contains the result of the a/d con- version. when the a/d conversion is completed, the result is loaded into the adres register, the go/done bit (adcon0<2>) is cleared, and a/d interrupt ?g bit adif is set. the block diagrams of the a/d module are shown in figure 13-5 and figure 13-6. after the a/d module has been con?ured as desired, the selected channel must be sampled before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine sample time, see section 13.1. after this sample time has elapsed the a/d conversion can be started. the following steps should be followed for doing an a/d conversion: 1. con?ure the a/d module: con?ure analog pins / voltage reference / and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon0) turn on a/d module (adcon0) 2. con?ure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required sampling time. 4. start conversion: set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result register (adres), clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is de?ed as t ad . a minimum wait of 2t ad is required before next sampling starts. figure 13-5: a/d block diagram, PIC16C70/71/71a (input voltage) v in v ref (reference voltage) v dd pcfg1:pcfg0 chs1:chs0 00 or 10 or 11 01 ra3/an3/v ref ra0/an0 ra2/an2 ra1/an1 11 10 01 00 a/d converter
1995 microchip technology inc. ds30390b-page 113 pic16c7x figure 13-6: a/d block diagram, pic16c72/73/73a/74/74a (input voltage) v in v ref (reference voltage) v dd pcfg2:pcfg0 chs2:chs0 000 or 010 or 100 001 or 011 or 101 re2/an7 (1) re1/an6 (1) re0/an5 (1) ra5/an4 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 111 110 101 100 011 010 001 000 a/d converter note 1: not available on pic16c72/73/73a.
pic16c7x ds30390b-page 114 1995 microchip technology inc. 13.1 a /d sampling requirements for the a/d converter to meet its speci?d accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 13-7. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 13-7. the maximum recommended impedance for analog sources is 10 k w . after the analog input channel is selected (changed) this sam- pling must be done before the conversion can be started. to calculate the minimum sampling time, equation 13- 1 may be used. this equation assumes that 1/2 lsb error is used (512 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its speci?d resolution. equation 13-1: a/d minimum charging time v hold = (v ref - (v ref /512)) ?(1 - e (-tc/c hold (r ic + r ss + r s )) ) or tc = -(51.2 pf)(1 k w + r ss + r s ) ln(1/511) example 13-1 shows the calculation of the minimum required sample time t smp . this calculation is based on the following system assumptions. rs = 10 k w 1/2 lsb error v dd = 5v ? rss = 7 k w temp (system max.) = 50 c v hold = 0 @ t = 0 applicable devices 70 71 71a 72 73 73a 74 74a example 13-1: calculating the minimum required sample time t smp = ampli?r settling time + holding capacitor charging time + temperature coef?ient t smp =5 m s + tc + [(temp - 25 c)(0.05 m s/ c)] t c =-c hold (r ic + r ss + r s ) ln(1/512) -51.2 pf (1 k w + 7 k w + 10 k w ) ln(0.0020) -51.2 pf (18 k w ) ln(0.0020) -0.921 m s (-6.2146) 5.724 m s t smp =5 m s + 5.724 m s + [(50 c - 25 c)(0.05 m s/ c)] 10.724 m s + 1.25 m s 11.974 m s note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. note 2: the charge holding capacitor (c hold ) is not discharged after each conversion. note 3: the maximum recommended impedance for analog sources is 10 k w . this is required to meet the pin leakage speci? cation. note 4: after a conversion has completed, a 2.0 t ad delay must complete before sam- pling can begin again. during this time the holding capacitor is not connected to the selected a/d input channel. figure 13-7: analog input model c pin va rs rax 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 ( k w ) v dd = 51.2 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
1995 microchip technology inc. ds30390b-page 115 pic16c7x 13.2 selecting the a /d con ver sion cloc k the a/d conversion time per bit is de?ed as t ad . the a/d conversion requires 9.5 t ad per 8-bit conversion. the source of the a/d conversion clock is software selected. the four possible options for t ad are: ?t osc ?t osc 32t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of: 2.0 m s for the pic16c71 1.6 m s for all other pic16c7x devices table 13-2 and table 13-1 show the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. applicable devices 70 71 71a 72 73 73a 74 74a 13.3 conf iguring analog p or t pins the adcon1, trisa, and trise registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (out- put), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. applicable devices 70 71 71a 72 73 73a 74 74a note 1: when reading the port register, all pins con?ured as analog input channel will read as cleared (a low level). pins con?- ured as digital inputs, will convert an ana- log input. analog levels on a digitally con?ured input will not affect the conver- sion accuracy. note 2: analog levels on any pin that is de?ed as a digital input (including the an7:an0 pins), may cause the input buffer to con- sume current that is out of the devices speci?ation. table 13-1: t ad vs. device operating frequencies, pic16c71 table 13-2: t ad vs. device operating frequencies, PIC16C70/71a/72/73/73a/74/74a ad clock source (t ad ) device frequency operation adcs1:adcs0 20 mhz 16 mhz 4 mhz 1 mhz 333.33 khz 2t osc 00 100 ns (2) 125 ns (2) 500 ns (2) 2.0 m s6 m s 8t osc 01 400 ns (2) 500 ns (2) 2.0 m s 8.0 m s 24 m s (3) 32t osc 10 1.6 m s (2) 2.0 m s 8.0 m s 32.0 m s (3) 96 m s (3) rc 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) 2 - 6 m s (1) note 1: the rc source has a typical t ad time of 4 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: while in rc mode, with device frequency above 1 mhz, conversion accuracy is out of speci?ation. ad clock source (t ad ) device frequency operation adcs1:adcs0 20 mhz 5 mhz 1.25 mhz 333.33 khz 2t osc 00 100 ns (2) 400 ns (2) 1.6 m s6 m s 8t osc 01 400 ns (2) 1.6 m s 6.4 m s 24 m s (3) 32t osc 10 1.6 m s 6.4 m s 25.6 m s (3) 96 m s (3) rc 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) note 1: the rc source has a typical t ad time of 4 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: while in rc mode, with device frequency above 1 mhz, conversion accuracy is out of speci?ation.
pic16c7x ds30390b-page 116 1995 microchip technology inc. 13.4 a /d con ver sions example 13-2 and example 13-3 show how to perform an a/d conversion. the ra pins are con?ured as ana- log inputs. the analog reference (v ref ) is the device v dd . the a/d interrupt is enabled, and the a/d conver- sion clock is f rc . the conversion is performed on the ra0 channel. applicable devices 70 71 71a 72 73 73a 74 74a clearing the go/done bit during a conversion will abort the current conversion. the adres register will not be updated with the partially completed a/d con- version sample. that is, the adres register will con- tinue to contain the value of the last completed conversion (or the last value written to the adres reg- ister). after the a/d conversion is aborted, a 2t ad wait is required before the next sampling is started. after this 2t ad wait, sampling is automatically started on the selected channel. note: the go/done bit should not be set in the same instruction that turns on the a/d. example 13-2: doing an a/d conversion (PIC16C70/71/71a) bsf status, rp0 ; select page 1 clrf adcon1 ; configure a/d inputs bcf status, rp0 ; select page 0 movlw 0xc1 ; rc clock, a/d is on, channel 0 is selected movwf adcon0 ; bsf intcon, adie ; enable a/d interrupt bsf intcon, gie ; enable all interrupts ; ; ensure that the required sampling time for the selected input channel has elapsed. ; then the conversion may be started. ; bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done bit : ; is cleared upon completion of the a/d conversion. example 13-3: doing an a/d conversion (pic16c72/73/73a/74/74a) bsf status, rp0 ; select page 1 clrf adcon1 ; configure a/d inputs bsf pie1, adie ; enable a/d interrupts bcf status, rp0 ; select page 0 movlw 0xc1 ; rc clock, a/d is on, channel 0 is selected movwf adcon0 ; bcf pir1, adif ; clear a/d interrupt flag bit bsf intcon, peie ; enable peripheral interrupts bsf intcon, gie ; enable all interrupts ; ; ensure that the required sampling time for the selected input channel has elapsed. ; then the conversion may be started. ; bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done bit : ; is cleared upon completion of the a/d conversion.
1995 microchip technology inc. ds30390b-page 117 pic16c7x 13.4.1 faster conversion - lower resolution trade-off not all applications require a result with 8-bits of reso- lution, but may instead require a faster conversion time. the a/d module allows users to make the trade- off of conversion speed to resolution. regardless of the resolution required, the sampling time is the same. to speed up the conversion, the clock source of the a/d module may be switched so that the t ad time violates the minimum speci?d time (see the applicable electri- cal speci?ation). once the t ad time violates the mini- mum speci?d time, all the following a/d result bits are not valid (see a/d conversion timing in the electrical speci?ations section.) the clock sources may only be switched between the three oscillator versions (cannot be switched from/to rc). the equation to determine the time before the oscillator can be switched is as fol- lows: conversion time = 2t ad + n? ad + (8 - n)(2t osc ) where: n = number of bits of resolution required. since the t ad is based from the device oscillator, the user must use some method (a timer, software loop, etc.) to determine when the a/d oscillator may be changed. example 13-4 shows a comparison of time required for a conversion with 4-bits of resolution, ver- sus the 8-bit resolution conversion. the example is for devices operating at 20 mhz and 16 mhz (the a/d clock is programmed for 32t osc ), and assumes that immediately after 6t ad , the a/d clock is programmed for 2t osc . the 2t osc violates the minimum t ad time since the last 4-bits will not be converted to correct values. example 13-4: 4-bit vs. 8-bit conversion times freq. (mhz) (1) resolution 4-bit 8-bit t ad 20 1.6 m s 1.6 m s 16 2.0 m s 2.0 m s t osc 20 50 ns 50 ns 16 62.5 ns 62.5 ns 2t ad + n? ad + (8 - n)(2t osc ) 20 10 m s 16 m s 16 12.5 m s 20 m s note 1: the pic16c71 has a minimum t ad time of 2.0 m s. all other pic16c7x devices have a minimum t ad time of 1.6 m s.
pic16c7x ds30390b-page 118 1995 microchip technology inc. 13.5 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switching noise from the conversion. when the conver- sion is completed the go/done bit will be cleared, and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d mod- ule will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 13.6 a/d accurac y/err or the overall accuracy of the a/d is less than 1 lsb for v dd = 5v 10% and the analog v ref = v dd . this over- all accuracy includes offset error, full scale error, and integral error. the a/d converter is guaranteed to be monotonic. the resolution and accuracy may be less when either the analog reference (v dd ) is less than 5.0v or when the analog reference (v ref ) is less than v dd . the maximum pin leakage current is 5 m a. in systems where the device frequency is low, use of the a/d rc clock derived from the device oscillator, is preferred. at moderate to high frequencies, t ad should be derived from the device oscillator. t ad must not vio- late the minimum and should be 8 m s for preferred operation. this is because t ad , when derived from t osc , is kept away from on-chip phase clock transi- tions. this reduces, to a large extent, the effects of dig- ital switching noise. this is not possible with the rc derived clock. the loss of accuracy due to digital switching noise can be signi?ant if many i/o pins are active. applicable devices 70 71 71a 72 73 73a 74 74a note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to perform an a/d conversion in sleep, the go/done bit must be set, followed by the sleep instruc- tion. applicable devices 70 71 71a 72 73 73a 74 74a in systems where the device will enter sleep mode after the start of the a/d conversion, the rc clock source selection is required. in this mode, the digital noise from the modules in sleep are stopped. this method gives high accuracy. 13.7 eff ect s of a reset a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion is aborted. the value that is in the adres register is not modi?d for a power-on reset. the adres register will contain unknown data after a power-on reset. 13.8 use of the ccp t rig g er an a/d conversion can be started by the ?pecial event trigger?of the ccp2 module (ccp1 on the pic16c72 only). this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be programmed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion, and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d sampling period with minimal software overhead (mov- ing the adres to the desired location). the appropri- ate analog input channel must be selected and the minimum sampling done before the ?pecial event trig- ger?sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the ?pecial event trigger?will be ignored by the a/d module, but will still reset the timer1 counter. applicable devices 70 71 71a 72 73 73a 74 74a applicable devices 70 71 71a 72 73 73a 74 74a note: in the pic16c72 the "special event trigger" is implemented in the ccp1 module.
1995 microchip technology inc. ds30390b-page 119 pic16c7x 13.9 connection considerations if the input voltage exceeds the rail values (v ss or v dd ) by greater than 0.2v, then the accuracy of the conver- sion is out of speci?ation. an external rc ?ter is sometimes added for anti-alias- ing of the input signal. the r component should be selected to ensure that the total source impedance is kept under the 10 k w recommended speci?ation. any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. 13.10 t ransf er function the ideal transfer function of the a/d converter is as fol- lows: the first transition occurs when the analog input voltage (v ain ) is 1 lsb (or analog v ref / 256) (figure 13-8). applicable devices 70 71 71a 72 73 73a 74 74a note: for the PIC16C70/71/71a, care must be taken when using the ra0 pin in a/d conversions due to its proximity to the osc1 pin. applicable devices 70 71 71a 72 73 73a 74 74a figure 13-8: a/d transfer function digital code output ffh feh 04h 03h 02h 01h 00h 0.5 lsb 1 lsb 2 lsb 3 lsb 4 lsb 255 lsb 256 lsb (full scale) analog input voltage figure 13-9: flowchart of a/d operation sample adon = 0 adon = 0? go = 0? a/d clock go = 0 adif = 0 abort conversion sleep power-down a/d wait 2 t ad wake-up yes no yes no no yes finish conversion go = 0 adif = 1 device in no yes finish conversion go = 0 adif = 1 wait 2 t ad stay in sleep selected channel = rc? sleep no yes instruction? start of a/d conversion delayed 1 instruction cycle from sleep? power-down a/d yes no wait 2 t ad finish conversion go = 0 adif = 1 sleep?
pic16c7x ds30390b-page 120 1995 microchip technology inc. table 13-3: summary of a/d registers, PIC16C70/71/71a table 13-4: summary of a/d registers, pic16c72 table 13-5: summary of a/d registers, pic16c73/73a/74/74a address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0bh/8bh intcon gie adie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 89h adres a/d result register xxxx xxxx uuuu uuuu 08h adcon0 adcs1 adcs0 chs1 chs0 go/done adif adon 00-0 0000 00-0 0000 88h adcon1 pcfg1 pcfg0 ---- --00 ---- --00 05h porta ra4 ra3 ra2 ra1 ra0 ---x xxxx ---u uuuu 85h trisa trisa4 trisa3 trisa2 trisa1 trisa0 ---1 1111 ---1 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done adon 0000 00-0 0000 00-0 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 05h porta ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu 85h trisa trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por bor value on all other resets 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0dh pir2 ccp2if ---- ---0 ---- ---0 8dh pie2 ccp2ie ---- ---0 ---- ---0 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done adon 0000 00-0 0000 00-0 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 05h porta ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu 85h trisa trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 09h porte re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode trise2 trise1 trise0 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion. note 1: bits pspie and pspif are reserved on the pic6c73/73a, always maintain these bits clear.
1995 microchip technology inc. ds30390b-page 121 pic16c7x 14.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits to deal with the needs of real- time applications. the pic16cxx family has a host of such features intended to maximize system reliability, minimize cost through elimination of external compo- nents, provide power saving operating modes and offer code protection. these are: osc selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) sleep code protection id locations in-circuit serial programming the pic16cxx has a watchdog timer which can be shut off only through con?uration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a ?ed delay of 72 ms (nominal) on power-up only, applicable devices 70 71 71a 72 73 73a 74 74a designed to keep the part in reset while the power sup- ply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to ? the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of con?uration bits are used to select various options. 14.1 c on guration bits the con?uration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device con?urations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space. in fact, it belongs to the special test/con?uration memory space (2000h - 3fffh), which can be accessed only during program- ming. applicable devices 70 71 71a 72 73 73a 74 74a figure 14-1: configuration word for pic16c71 cp0 pwrte wdte f0sc1 f0sc0 register: config address 2007h bit13 bit0 bit 13-5: unimplemented : read as '1' bit 4: cp0 : code protection bit 1 = code protection off 0 = all memory is code protected, but 00h - 3fh is writable bit 3: pwrte : power-up timer enable bit 1 = power-up timer enabled 0 = power-up timer disabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator this document was created with framemake r404
pic16c7x ds30390b-page 122 1995 microchip technology inc. figure 14-2: configuration word for PIC16C70/71a figure 14-3: configuration word for pic16c73/74 cp0 cp0 cp0 cp0 cp0 cp0 cp0 boden cp0 cp0 pwr te wdte f0sc1 f0sc0 register: config address 2007h bit13 bit0 bit 13-7 cp0 : code protection bits (2) 5-4: 1 = code protection off 0 = all memory is code protected, but 00h - 3fh is writable bit 6: boden : brown-out reset enable bit (1) 1 = bor enabled 0 = bor disabled bit 3: pwr te : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables power-up timer (pwrt) regardless of the value of bit p wr t e . ensure the power-up timer is enabled anytime brown-out reset is enabled. 2: all of the cp0 bits have to be given the same value to enable the code protection scheme listed. cp1 cp0 pwrte wdte f0sc1 f0sc0 register: config address 2007h bit13 bit0 bit 13-5: unimplemented : read as '1' bit 4: cp1:cp0 : code protection bits 11 = code protection off 10 = upper half of program memory code protected 01 = upper 3/4th of program memory code protected 00 = all memory is code protected bit 3: pwrte : power-up timer enable bit 1 = power-up timer enabled 0 = power-up timer disabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator
1995 microchip technology inc. ds30390b-page 123 pic16c7x figure 14-4: configuration word for pic16c72/73a/74a cp1 cp0 cp1 cp0 cp1 cp0 boden cp1 cp0 pwr te wdte f0sc1 f0sc0 register: config address 2007h bit13 bit0 bit 13-8 cp1:cp0 : code protection bits (2) 5-4: 11 = code protection off 10 = upper half of program memory code protected 01 = upper 3/4th of program memory code protected 00 = all memory is code protected bit 7: unimplemented : read as '1' bit 6: boden : brown-out reset enable bit (1) 1 = bor enabled 0 = bor disabled bit 3: pwr te : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables power-up timer (pwrt) regardless of the value of bit p wr t e . ensure the power-up timer is enabled anytime brown-out reset is enabled. 2: all of the cp1:cp0 pairs have to be given the same value to enable the code protection scheme listed. 14.2 oscillator con gurations 14.2.1 oscillator types the pic16cxx can be operated in four different oscil- lator modes. the user can program two con?uration bits (fosc1 and fosc0) to select one of these four modes: lp low power crystal xt crystal/resonator hs high speed crystal/resonator rc resistor/capacitor 14.2.2 crystal oscillator/ceramic resonators in xt, lp or hs modes a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 14-5). the pic16cxx oscillator design requires the use of a par- allel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers speci?a- tions. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1/ clkin pin (figure 14-6). applicable devices 70 71 71a 72 73 73a 74 74a figure 14-5: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 14-6: external clock input operation (hs, xt or lp osc configuration) c1 c2 xtal osc2 note1 osc1 r f sleep to internal logic pic16cxx rs see table 14-1, table 14-2, table 14-3 and table 14-4 for recommended values of c1 and c2. note 1: a series resistor may be required for at strip cut crystals. 2: for the PIC16C70/71/71a the buffer is on the osc2 pin, all other devices have the buffer on the osc1 pin. (2) (2) to internal logic osc1 osc2 open clock from ext. system pic16cxx
pic16c7x ds30390b-page 124 1995 microchip technology inc. table 14-1: ceramic resonators pic16c71 table 14-2: capacitor selection for crystal oscillator for pic16c71 ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 47 - 100 pf 15 - 68 pf 15 - 68 pf 47 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 15 - 68 pf 10 - 47 pf 15 - 68 pf 10 - 47 pf note : recommended values of c1 and c2 are identical to the ranges tested table. higher capacitance increases the stability of oscilla- tor but also increases the start-up time. these val- ues are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. mode freq osc1 osc2 lp 32 khz 200 khz 33 - 68 pf 15 - 47 pf 33 - 68 pf 15 - 47 pf xt 100 khz 500 khz 1 mhz 2 mhz 4 mhz 47 - 100 pf 20 - 68 pf 15 - 68 pf 15 - 47 pf 15 - 33 pf 47 - 100 pf 20 - 68 pf 15 - 68 pf 15 - 47 pf 15 - 33 pf hs 8 mhz 20 mhz 15 - 47 pf 15 - 47 pf 15 - 47 pf 15 - 47 pf note : higher capacitance increases the stability of oscil- lator but also increases the start-up time. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level speci?a- tion. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. table 14-3: ceramic resonators PIC16C70/71a/72/73/73a/74/ 74a table 14-4: capacitor selection for crystal oscillator for PIC16C70/71a/72/73/73a/ 74/74a ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf note : recommended values of c1 and c2 are identical to the ranges tested table. higher capacitance increases the stability of oscil- lator but also increases the start-up time. these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. mode freq osc1 osc2 lp 32 khz (1) 200 khz 15 - 47 pf 15 - 33 pf 15 - 47 pf 15 - 33 pf xt 100 khz 500 khz 1 mhz 2 mhz 4 mhz 47 - 100 pf 20 - 68 pf 15 - 68 pf 15 - 47 pf 15 - 33 pf 47 - 100 pf 20 - 68 pf 15 - 68 pf 15 - 47 pf 15 - 33 pf hs 8 mhz 20 mhz 15 - 47 pf 15 - 47 pf 15 - 47 pf 15 - 47 pf note : higher capacitance increases the stability of oscil- lator but also increases the start-up time. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level speci?a- tion. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. note 1: for v dd > 4.5v, c1 = c2 ? 30 pf is recom- mended.
1995 microchip technology inc. ds30390b-page 125 pic16c7x 14.2.3 external crystal oscillator circuit either a prepackaged oscillator can be used or a simple oscillator circuit with ttl gates can be built. prepack- aged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. figure 14-7 shows implementation of a parallel reso- nant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a par- allel oscillator requires. the 4.7 k w resistor provides the negative feedback for stability. the 10 k w potenti- ometer biases the 74as04 in the linear region. this could be used for external oscillator designs. figure 14-7: external parallel resonant crystal oscillator circuit figure 14-8 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental fre- quency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator cir- cuit. the 330 k w resistors provide the negative feed- back to bias the inverters in their linear region. figure 14-8: external series resonant crystal oscillator circuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 clkin to other devices 330 k w 74as04 74as04 pic16cxx clkin to other devices xtal 330 k w 74as04 0.1 m f 14.2.4 rc oscillator for timing insensitive applications the ?c?device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (rext) and capacitor (cext) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low cext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 14-9 shows how the r/c combina- tion is connected to the pic16cxx. for rext values below 2.2 k w , the oscillator operation may become unstable, or stop completely. for very high rext values (e.g. 1 m w ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend to keep rext between 3 k w and 100 k w . although the oscillator will operate with no external capacitor (cext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or pack- age lead frame capacitance. see characterization data for desired device for rc fre- quency variation from part to part due to normal pro- cess variation. the variation is larger for larger r (since leakage current variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). see characterization data for desired device for varia- tion of oscillator frequency due to v dd for given rext/ cext values as well as frequency variation due to oper- ating temperature for given r, c, and v dd values. the oscillator frequency, divided by 4, is available on the osc2/clkout pin, and can be used for test pur- poses or to synchronize other logic (see figure 3-5 for waveform). figure 14-9: rc oscillator mode osc2/clkout cext v dd rext v ss pic16cxx osc1 fosc/4 internal clock
pic16c7x ds30390b-page 126 1995 microchip technology inc. 14.3 reset the pic16cxx differentiates between various kinds of reset: power-on reset (por) mclr reset during normal operation mclr reset during sleep wdt reset (normal operation) brown-out reset (bor) (PIC16C70/71a/72/73a/ 74a only) some registers are not affected in any reset condition; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?eset state?on power-on reset (por), on the mclr and wdt reset, on mclr reset during sleep, and brown- out reset (bor). they are not affected by a wdt wake-up, which is viewed as the resumption of normal operation. the t o and pd bits are set or cleared differ- ently in different reset situations as indicated in applicable devices 70 71 71a 72 73 73a 74 74a table 14-7 and table 14-8. these bits are used in soft- ware to determine the nature of the reset. see table 14-10 for a full description of reset states of all registers. a simpli?d block diagram of the on-chip reset circuit is shown in figure 14-10. the PIC16C70/71a/72/73a/74a have a mclr noise ?ter in the mclr reset path. the ?ter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. figure 14-10: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip (1) rc osc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep see table 14-5 and table 14-6 for time- out situations. note 1: this is a separate oscillator from the rc oscillator of the clkin pin. 2: brown-out reset is implemented on the PIC16C70/71a/72/73a/74a only. brown-out reset (2) boden
1995 microchip technology inc. ds30390b-page 127 pic16c7x 14.4 p o wer -on reset (por), p o wer -up timer (pwr t) and oscillator star t-up timer (ost) , br o wn-out reset ( bo r) 14.4.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.5v - 2.1v). to take advantage of the por, just tie the mclr pin directly (or through a resistor) to v dd . this will elimi- nate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is speci?d. see electrical speci?ations for details. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be meet to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for additional information, refer to application note an607, " power-up trouble shooting ." 14.4.2 power-up timer (pwrt) the power-up timer provides a ?ed 72 ms nominal time-out on power-up only, from the por. the power- up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrts time delay allows v dd to rise to an acceptable level. a con?uration bit is provided to enable/disable the pwrt. applicable devices 70 71 71a 72 73 73a 74 74a the power-up time delay will vary from chip to chip and due to v dd , temperature, and process variation. see dc parameters for details. 14.4.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures that the crystal oscil- lator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 14.4.4 brown-out reset (bor) a con?uration bit, boden, can disable (if clear/pro- grammed) or enable (if set) the brown-out reset cir- cuitry. if v dd falls below 4.0v (3.8v - 4.2v range) for greater than parameter #35, the brown-out situation will reset the chip. a reset may not occur if v dd falls below 4.0v for less than parameter #35. the chip will remain in brown-out reset until v dd rises above bv dd . the power-up timer will now be invoked and will keep the chip in reset an additional 72 ms. if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above bv dd , the power-up timer will execute a 72 ms reset. the power-up timer should always be enabled when brown-out reset is enabled. figure 14-11 shows typical brown-out situations. applicable devices 70 71 71a 72 73 73a 74 74a figure 14-11: brown-out situations 72 ms bv dd max. bv dd min. v dd internal reset bv dd max. bv dd min. v dd internal reset 72 ms <72 ms 72 ms bv dd max. bv dd min. v dd internal reset
pic16c7x ds30390b-page 128 1995 microchip technology inc. 14.4.5 time-out sequence on power-up the time-out sequence is as follows: first pwrt time-out is invoked after the por time delay has expired. then ost is activated. the total time-out will vary based on oscillator con?uration and the sta- tus of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 14-12, figure 14-13, and figure 14-14 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high will begin execution immediately (figure 14-13). this is useful for testing purposes or to synchronize more than one pic16cxx device operat- ing in parallel. table 14-9 shows the reset conditions for some special function registers, while table 14-10 shows the reset conditions for all the registers. 14.4.6 power control/status register (pcon) the power control/status register, pcon has up to 2 bits, depending upon the device. bit0 is not imple- mented on the pic16c73 or pic16c74. bit0 is brown-out reset status bit, bo r . bit bo r is unknown on a power-on reset. it must then be set by the user and checked on subsequent resets to see if bit bo r cleared, indicating a bor occurred. the bo r bit is a "don? care" bit and is not necessarily predictable if the brown-out reset circuitry is disabled (by clearing bit boden in the con?uration word). bit1 is power-on reset status bit por . it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset. applicable devices 70 71 71a 72 73 73a 74 74a table 14-5: time-out in various situations, pic16c71/73/74 table 14-6: time-out in various situations, PIC16C70/71a/72/73a/74a table 14-7: status bits and their significance, pic16c71/73/74 table 14-8: status bits and their significance, PIC16C70/71a/72/73a/74a oscillator con?uration power-up wake-up from sleep pwrte = 1 pwrte = 0 xt, hs, lp 72 ms + 1024t osc 1024t osc 1024 t osc rc 72 ms oscillator con?uration power-up brown-out wake-up from sleep pwr te = 0 pwr te = 1 xt, hs, lp 72 ms + 1024t osc 1024t osc 72 ms + 1024t osc 1024t osc rc 72 ms 72 ms por (1) t o pd 011 power-on reset 00x illegal, t o is set on por 0x0 illegal, pd is set on por 101 wdt reset 100 wdt wake-up 111 mclr reset during normal operation 110 mclr reset during sleep or interrupt wake-up from sleep note 1: bit por is not implemented on the pic16c71. por bo r t o pd 0x11 power-on reset 0x0x illegal, t o is set on por 0xx0 illegal, pd is set on por 10xx brown-out reset 1101 wdt reset 1100 wdt wake-up 1111 mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep
1995 microchip technology inc. ds30390b-page 129 pic16c7x table 14-9: reset condition for special registers condition program counter status register pcon register PIC16C70/71a pcon register pic16c73/74 pcon register pic16c72/73a/74a power-on reset 000h 0001 1xxx ---- --0x ---- --0- ---- --0x mclr reset during normal operation 000h 0001 1uuu ---- --uu ---- --u- ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu ---- --u- ---- --uu wdt reset 000h 0000 1uuu ---- --uu ---- --u- ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu ---- --u- ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 n/a ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu ---- --u- ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). table 14-10: initialization conditions for all registers register applicable devices power-on reset, brown-out reset mclr resets wdt reset wake-up via wdt or interrupt w 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu indf 70 71 71a 72 73 73a 74 74a n/a n/a n/a tmr0 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu pcl 70 71 71a 72 73 73a 74 74a 0000h 0000h pc + 1 (2) status 70 71 71a 72 73 73a 74 74a 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu porta 70 71 71a 72 73 73a 74 74a ---x xxxx ---u uuuu ---u uuuu 70 71 71a 72 73 73a 74 74a --xx xxxx --uu uuuu --uu uuuu portb 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu portc 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu portd 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu porte 70 71 71a 72 73 73a 74 74a ---- -xxx ---- -uuu ---- -uuu pclath 70 71 71a 72 73 73a 74 74a ---0 0000 ---0 0000 ---u uuuu intcon 70 71 71a 72 73 73a 74 74a 0000 000x 0000 000u uuuu uuuu (1) pir1 70 71 71a 72 73 73a 74 74a -0-- 0000 -0-- 0000 -u-- uuuu (1) 70 71 71a 72 73 73a 74 74a -000 0000 -000 0000 -uuu uuuu (1) 70 71 71a 72 73 73a 74 74a 0000 0000 0000 0000 uuuu uuuu (1) pir2 70 71 71a 72 73 73a 74 74a ---- ---0 ---- ---0 ---- ---u (1) tmr1l 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu t1con 70 71 71a 72 73 73a 74 74a --00 0000 --uu uuuu --uu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 14-9 for reset value for speci? condition.
pic16c7x ds30390b-page 130 1995 microchip technology inc. tmr2 70 71 71a 72 73 73a 74 74a 0000 0000 0000 0000 uuuu uuuu t2con 70 71 71a 72 73 73a 74 74a -000 0000 -000 0000 -uuu uuuu sspbuf 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu sspcon 70 71 71a 72 73 73a 74 74a 0000 0000 0000 0000 uuuu uuuu ccpr1l 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 70 71 71a 72 73 73a 74 74a --00 0000 --00 0000 --uu uuuu rcsta 70 71 71a 72 73 73a 74 74a 0000 -00x 0000 -00x uuuu -uuu txreg 70 71 71a 72 73 73a 74 74a 0000 0000 0000 0000 uuuu uuuu rcreg 70 71 71a 72 73 73a 74 74a 0000 0000 0000 0000 uuuu uuuu ccpr2l 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu ccpr2h 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 70 71 71a 72 73 73a 74 74a 0000 0000 0000 0000 uuuu uuuu adres 70 71 71a 72 73 73a 74 74a xxxx xxxx uuuu uuuu uuuu uuuu adcon0 70 71 71a 72 73 73a 74 74a 00-0 0000 00-0 0000 uu-u uuuu 70 71 71a 72 73 73a 74 74a 0000 00-0 0000 00-0 uuuu uu-u option 70 71 71a 72 73 73a 74 74a 1111 1111 1111 1111 uuuu uuuu trisa 70 71 71a 72 73 73a 74 74a ---1 1111 ---1 1111 ---u uuuu 70 71 71a 72 73 73a 74 74a --11 1111 --11 1111 --uu uuuu trisb 70 71 71a 72 73 73a 74 74a 1111 1111 1111 1111 uuuu uuuu trisc 70 71 71a 72 73 73a 74 74a 1111 1111 1111 1111 uuuu uuuu trisd 70 71 71a 72 73 73a 74 74a 1111 1111 1111 1111 uuuu uuuu trise 70 71 71a 72 73 73a 74 74a 0000 -111 0000 -111 uuuu -uuu pie1 70 71 71a 72 73 73a 74 74a -0-- 0000 -0-- 0000 -u-- uuuu 70 71 71a 72 73 73a 74 74a -000 0000 -000 0000 -uuu uuuu 70 71 71a 72 73 73a 74 74a 0000 0000 0000 0000 uuuu uuuu pie2 70 71 71a 72 73 73a 74 74a ---- ---0 ---- ---0 ---- ---u pcon 70 71 71a 72 73 73a 74 74a ---- --0- ---- --u- ---- --u- 70 71 71a 72 73 73a 74 74a ---- --0u ---- --uu ---- --uu pr2 70 71 71a 72 73 73a 74 74a 1111 1111 1111 1111 1111 1111 sspadd 70 71 71a 72 73 73a 74 74a 0000 0000 0000 0000 uuuu uuuu sspstat 70 71 71a 72 73 73a 74 74a --00 0000 --00 0000 --uu uuuu txsta 70 71 71a 72 73 73a 74 74a 0000 -010 0000 -010 uuuu -uuu spbrg 70 71 71a 72 73 73a 74 74a 0000 0000 0000 0000 uuuu uuuu adcon1 70 71 71a 72 73 73a 74 74a ---- --00 ---- --00 ---- --uu 70 71 71a 72 73 73a 74 74a ---- -000 ---- -000 ---- -uuu table 14-10: initialization conditions for all registers (cont.d) register applicable devices power-on reset, brown-out reset mclr resets wdt reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 14-9 for reset value for speci? condition.
1995 microchip technology inc. ds30390b-page 131 pic16c7x figure 14-12: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 14-13: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 14-14: time-out sequence on power-up (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset
pic16c7x ds30390b-page 132 1995 microchip technology inc. figure 14-15: external power-on reset circuit (for slow v dd power-up) note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k w is recommended to make sure that voltage drop across r does not violate the devices electrical speci?ation. 3: r1 = 100 w to 1 k w will limit any current ?wing into mclr from external capacitor c in the event of mclr /v pp pin break- down due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic16cxx figure 14-16: external brown-out protection circuit 1 figure 14-17: external brown-out protection circuit 2 note 1: this circuit will activate reset when v dd goes below (vz + 0.7v) where vz = zener voltage. 2: internal brown-out detection on the PIC16C70/71a/72/73a/74a should be dis- abled when using this circuit. 3: resistors should be adjusted for the char- acteristics of the transistor. v dd 33k 10k 40k v dd mclr pic16cxx note 1: this brown-out circuit is less expensive, albeit less accurate. transistor q1 turns off when v dd is below a certain level such that: 2: internal brown-out detection on the PIC16C70/71a/72/73a/74a should be disabled when using this circuit. 3: resistors should be adjusted for the characteristics of the transistor. v dd r1 r1 + r2 = 0.7v v dd r2 40k v dd mclr pic16cxx r1 q1
1995 microchip technology inc. ds30390b-page 133 pic16c7x 14.5 interrupts the pic16c7x family has up to 12 sources of interrupt: applicable devices 70 71 71a 72 73 73a 74 74a interrupt sources applicable devices external interrupt rb0/int 70 71 71a 72 73 73a 74 74a tmr0 over?w interrupt 70 71 71a 72 73 73a 74 74a portb change interrupts (pins rb7:rb4) 70 71 71a 72 73 73a 74 74a a/d interrupt 70 71 71a 72 73 73a 74 74a tmr1 over?w interrupt 70 71 71a 72 73 73a 74 74a tmr2 matches period interrupt 70 71 71a 72 73 73a 74 74a ccp1 interrupt 70 71 71a 72 73 73a 74 74a ccp2 interrupt 70 71 71a 72 73 73a 74 74a usart receive 70 71 71a 72 73 73a 74 74a usart transmit 70 71 71a 72 73 73a 74 74a synchronous serial port interrupt 70 71 71a 72 73 73a 74 74a parallel slave port read/write interrupt 70 71 71a 72 73 73a 74 74a the interrupt control register (intcon) records individ- ual interrupt requests in ?g bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. when bit gie is enabled, and an interrupts ?g bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. the ?eturn from interrupt?instruction, retfie , exits the interrupt routine as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 over?w interrupt ?gs are contained in the intcon register. the peripheral interrupt ?gs are contained in the spe- cial function registers pir1 and pir2. the correspond- ing interrupt enable bits are contained in special function registers pie1 and pie2, and the peripheral interrupt enable bit is contained in special function reg- ister intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ?g bits. the interrupt ?g bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. note: individual interrupt ?g bits are set regard- less of the status of their corresponding mask bit or the gie bit. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs (figure 14- 22). the latency is the same for one or two cycle instructions. individual interrupt ?g bits are set regard- less of the status of their corresponding mask bit or the gie bit. note: for the pic16c71/73/74 only, if an interrupt occurs while the global inter- rupt enable (gie) bit is being cleared, the gie bit may unintentionally be re-enabled by the users interrupt service routine (the retfie instruction). the events that would cause this to occur are: 1. an instruction clears the gie bit while an interrupt is acknowledged. 2. the program branches to the interrupt vector and executes the interrupt ser- vice routine. 3. the interrupt service routine com- pletes with the execution of the ret- fie instruction. this causes the gie bit to be set (enables interrupts), and the program returns to the instruction after the one which was meant to dis- able interrupts. perform the following to ensure that inter- rupts are globally disabled: loop bcf intcon, gie ; disable global ; interrupt bit btfsc intcon, gie ; global interrupt ; disabled? goto loop ; no, try again : ; yes, continue ; with program ; flow
pic16c7x ds30390b-page 134 1995 microchip technology inc. figure 14-18: interrupt logic for PIC16C70/71/71a figure 14-19: interrupt logic for pic16c72 figure 14-20: interrupt logic for pic16c73/73a rbif rbie t0if t0ie intf inte gie adie wakeup (if in sleep mode) interrupt to cpu adif tmr1if tmr1ie tmr2if tmr2ie ccp1if ccp1ie adif adie sspif sspie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu peif tmr1if tmr1ie tmr2if tmr2ie ccp1if ccp1ie ccp2if ccp2ie adif adie rcif rcie sspif sspie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu peif txif txie
1995 microchip technology inc. ds30390b-page 135 pic16c7x figure 14-21: interrupt logic for pic16c74/74a figure 14-22: int pin interrupt timing tmr1if tmr1ie tmr2if tmr2ie ccp1if ccp1ie ccp2if ccp2ie adif adie txif txie rcif rcie sspif sspie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu peif pspie pspif q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf ?g (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed interrupt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dummy cycle inst (pc) 1 4 5 1 note 1: intf ?g is sampled here (every q1). 2: interrupt latency = 3-4 tcy where tcy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in rc oscillator mode. 4: for minimum width of int pulse, refer to ac specs. 5: intf is enabled to be set anytime during the q4-q1 cycles. 2 3
pic16c7x ds30390b-page 136 1995 microchip technology inc. 14.5.1 int interrupt external interrupt on rb0/int pin is edge triggered: either rising if bit intedg (option<6>) is set, or fall- ing, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, ?g bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service rou- tine before re-enabling this interrupt. the int interrupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global interrupt enable bit gie decides whether or not the pro- cessor branches to the interrupt vector following wake- up. see section 14.8 for details on sleep mode. 14.5.2 tmr0 interrupt an over?w (ffh ? 00h) in the tmr0 register will set ?g bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>). (section 7.0) 14.5.3 portb intcon change an input change on portb <7:4> sets ?g bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<4>). (section 5.2) 14.6 conte xt sa ving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt i.e., w register and status register. this will have to be implemented in software. example 14-1 and example 14-2 store and restore the status and w registers. for pic16c72/73/73a/74/ 74a, the register, w_temp, must be de?ed in both banks and must be de?ed at the same offset from the bank base address (i.e., if w_temp is de?ed at 0x20 in bank 0, it must also be de?ed at 0xa0 in bank 1). for PIC16C70/71/71a, the user register, status_temp, must be de?ed in bank 0. the example: a) stores the w register. b) stores the status register in bank 0. c) executes the isr code. d) restores the status register (and bank select bit). e) restores the w register. note: for the pic16c71/73/74 only, if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the rbif inter- rupt ?g may not get set. applicable devices 70 71 71a 72 73 73a 74 74a example 14-1: saving status and w registers in ram (PIC16C70/71/71a) movwf w_temp ;copy w to temp register, could be bank one or zero swapf status,w ;swap status to be saved into w movwf status_temp ;save status to bank zero status_temp register : :(isr) : swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w example 14-2: saving status and w registers in ram (pic16c72/73/73a/74/74a) movwf w_temp ;copy w to temp register, could be bank one or zero swapf status,w ;swap status to be saved into w bcf status,rp0 ;change to bank zero, regardless of current bank movwf status_temp ;save status to bank zero status_temp register : :(isr) : swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
1995 microchip technology inc. ds30390b-page 137 pic16c7x 14.7 w atc hdog timer (wdt) the watchdog timer is as a free running on-chip rc oscillator which does not require any external compo- nents. this rc oscillator is separate from the rc oscil- lator of the osc1/clkin pin. that means that the wdt will run, even if the clock on the osc1/clkin and osc2/clkout pins of the device has been stopped, for example, by execution of a sleep instruction. dur- ing normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the wdt can be permanently disabled by clearing con?uration bit wdte (section 14.1). 14.7.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). the time-out periods vary with tempera- ture, v dd and process variations from part to part (see dc specs). if longer time-out periods are desired, a applicable devices 70 71 71a 72 73 73a 74 74a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control by writing to the option register. thus, time-out periods up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset condi- tion. the t o bit in the status register will be cleared upon a watchdog timer time-out. 14.7.2 wdt programming considerations it should also be taken into account that under worst case conditions (v dd = min., temperature = max., and max. wdt prescaler) it may take several seconds before a wdt time-out occurs. figure 14-23: watchdog timer block diagram figure 14-24: summary of watchdog timer registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h con?. bits (1) boden (1) cp1 cp0 pwrte (1) wdte fosc1 fosc0 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see figure 14-1, figure 14-2, figure 14-3, and figure 14-4 for operation of these bits. from tmr0 clock source (figure 7-6) to tmr0 (figure 7-6) postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option register. 8
pic16c7x ds30390b-page 138 1995 microchip technology inc. 14.8 p o wer - do wn mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the t o (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd , or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d, disable external clocks. pull all i/o pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by ?ating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 14.8.1 wake-up from sleep the device can wake up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change, or some peripheral interrupts. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a "wake-up". the t o and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on applicable devices 70 71 71a 72 73 73a 74 74a power-up is cleared when sleep is invoked. the t o bit is cleared if wdt time-out occurred (and caused wake- up). the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. ssp (start/stop) bit detect interrupt. 3. ssp transmit or receive in slave mode (spi/ i 2 c). 4. ccp capture mode interrupt. 5. parallel slave port read or write. 6. a/d conversion (when a/d clock source is rc). 7. special event trigger (timer1 in asynchronous mode using an external clock). 8. usart tx or rx (synchronous slave mode). other peripherals can not generate interrupts since during sleep, no on-chip q clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes-up from sleep, regardless of the source of wake-up. note: interrupts that are capable of waking the device from sleep will still set the individ- ual ?g bits regardless of the state of the global enable bit, gie. figure 14-25: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout(4) int pin intf ?g (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will continue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference.
1995 microchip technology inc. ds30390b-page 139 pic16c7x 14.9 pr ogram v eri cation/ code pr otection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for veri?ation purposes. 14.10 id locations four memory locations (2000h - 2003h) are designated as id locations where the user can store checksum or other code-identi?ation numbers. these locations are not accessible during normal execution but are read- able and writable during program/verify. it is recom- mended that only the 4 least signi?ant bits of id location are used. applicable devices 70 71 71a 72 73 73a 74 74a note: microchip does not recommend code pro- tecting windowed devices. applicable devices 70 71 71a 72 73 73a 74 74a 14.11 in-cir cuit serial pr ogramming pic16cxx microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent ?mware or a custom ?m- ware to be programmed. the device is placed into a program/verify mode by holding the rb6 and rb7 pins low while raising the mclr (v pp ) pin from v il to v ihh (see programming speci?ation). rb6 becomes the programming clock and rb7 becomes the programming data. both rb6 and rb7 are schmitt trigger inputs in this mode. after reset, to place the device into programming/verify mode, the program counter (pc) is at location 00h. a 6- bit command is then supplied to the device. depending on the command, 14-bits of program data are then sup- plied to or from the device, depending if the command was a load or a read. for complete details of serial pro- gramming, please refer to the pic16c6x/7x program- ming speci?ations (literature #ds30228). figure 14-26: typical in-circuit serial programming connection applicable devices 70 71 71a 72 73 73a 74 74a external connector signals to normal connections to normal connections pic16cxx v dd v ss mclr /v pp rb6 rb7 +5v 0v v pp clk data i/o v dd
pic16c7x ds30390b-page 140 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30390b-page 141 pic16c7x 15.0 instruction set summary each pic16cxx instruction is a 14-bit word divided into an opcode which speci?s the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxx instruction set summary in table 15-2 lists byte-oriented , bit-ori- ented , and literal and control operations. table 15-1 shows the opcode ?ld descriptions. for byte-oriented instructions, 'f' represents a ?e reg- ister designator and 'd' represents a destination desig- nator. the ?e register designator speci?s which ?e register is to be used by the instruction. the destination designator speci?s where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the ?e register speci?d in the instruction. for bit-oriented instructions, 'b' represents a bit ?ld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ?e in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 15-1: opcode field descriptions applicable devices 70 71 71a 72 73 73a 74 74a field description f register ?e address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit ?e register k literal ?ld, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in ?e register f. default is d = 1 label label name tos top of stack pc program counter pclath program counter high latch gie global interrupt enable bit wdt watchdog timer/counter to time-out bit pd power-down bit dest destination either the w register or the speci?d register ?e location [ ] options ( ) contents ? assigned to < > register bit ?ld ? in the set of i talics user de?ed term (font is courier) the instruction set is highly orthogonal and is grouped into three basic categories: byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop. one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 m s. table 15-2 lists the instructions recognized by the mpasm assembler. figure 15-1 shows the three general formats that the instructions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signi?s a hexadecimal digit. figure 15-1: general format for instructions note: to maintain upward compatibility with future pic16cxx products, do not use the option and tris instructions. byte-oriented ?e register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit ?e register address bit-oriented ?e register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit ?e register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only this document was created with framemake r404
pic16c7x ds30390b-page 142 1995 microchip technology inc. table 15-2: pic16cxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z t o , pd z t o , pd c,dc,z z note 1: when an i/o register is modi?d as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin con?ured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modi?d or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop.
1995 microchip technology inc. ds30390b-page 143 pic16c7x 15.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k ? (w) status affected: c, dc, z encoding: 11 111x kkkk kkkk description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w register . words: 1 cycles: 1 example addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d ? [0,1] operation: (w) + (f) ? (dest) status affected: c, dc, z encoding: 00 0111 dfff ffff description: add the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 example addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) ? (w) status affected: z encoding: 11 1001 kkkk kkkk description: the contents of w register are and?d with the eight bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 example andlw 0x5f before instruction w = 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .and. (f) ? (dest) status affected: z encoding: 00 0101 dfff ffff description: and the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 example andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02
pic16c7x ds30390b-page 144 1995 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 ? (f) status affected: none encoding: 01 00bb bfff ffff description: bit 'b' in register 'f' is cleared . words: 1 cycles: 1 example bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 ? (f) status affected: none encoding: 01 01bb bfff ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 example bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 01 10bb bfff ffff description: if bit 'b' in register 'f' is '0' then the next instruction is skipped. if bit 'b' is '0' then the next instruction fetched during the current instruction execution is discarded, and a nop is executed instead, making this a 2 cycle instruction . words: 1 cycles: 1(2) example here false true btfsc goto flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, pc = address true if flag<1>=1, pc = address false
1995 microchip technology inc. ds30390b-page 145 pic16c7x btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 01 11bb bfff ffff description: if bit 'b' in register 'f' is '1' then the next instruction is skipped. if bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example here false true btfsc goto flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, pc = address false if flag<1> = 1, pc = address true call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none encoding: 10 0kkk kkkk kkkk description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two cycle instruction. words: 1 cycles: 2 example here call there before instruction pc = address here after instruction pc = address there tos = address here+1 clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h ? (f) 1 ? z status affected: z encoding: 00 0001 1fff ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 example clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z encoding: 00 0001 0xxx xxxx description: w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example clrw before instruction w = 0x5a after instruction w = 0x00 z=1
pic16c7x ds30390b-page 146 1995 microchip technology inc. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? t o 1 ? pd status affected: t o , pd encoding: 00 0000 0110 0100 description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits t o and pd are set. words: 1 cycles: 1 example clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescaler = 0 t o =1 pd =1 comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d ? [0,1] operation: (f ) ? (dest) status affected: z encoding: 00 1001 dfff ffff description: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in w. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w = 0xec decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (dest) status affected: z encoding: 00 0011 dfff ffff description: decrement register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 example decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (dest); skip if result = 0 status affected: none encoding: 00 1011 dfff ffff description: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded. a nop is executed instead making it a two cycle instruction. words: 1 cycles: 1(2) example here decfsz cnt, 1 goto loop continue before instruction pc = address here after instruction cnt = cnt - 1 if cnt = 0, pc = address continue if cnt 1 0, pc = address here+1
1995 microchip technology inc. ds30390b-page 147 pic16c7x goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none encoding: 10 1kkk kkkk kkkk description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two cycle instruction. words: 1 cycles: 2 example goto there after instruction pc = address there incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (dest) status affected: z encoding: 00 1010 dfff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (dest), skip if result = 0 status affected: none encoding: 00 1111 dfff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded. a nop is executed instead making it a two cycle instruction . words: 1 cycles: 1(2) example here incfsz cnt, 1 goto loop continue before instruction pc = address here after instruction cnt = cnt + 1 if cnt= 0, pc = address continue if cnt 1 0, pc = address here +1 iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k ? (w) status affected: z encoding: 11 1000 kkkk kkkk description: the contents of the w register is or?d with the eight bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 example iorlw 0x35 before instruction w = 0x9a after instruction w = 0xbf z=1
pic16c7x ds30390b-page 148 1995 microchip technology inc. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .or. (f) ? (dest) status affected: z encoding: 00 0100 dfff ffff description: inclusive or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=1 movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k ? (w) status affected: none encoding: 11 00xx kkkk kkkk description: the eight bit literal 'k' is loaded into w register . the don? cares will assemble as 0s. words: 1 cycles: 1 example movlw 0x5a after instruction w = 0x5a movf move f syntax: [ label ] movf f,d operands: 0 f 127 d ? [0,1] operation: (f) ? (dest) status affected: z encoding: 00 1000 dfff ffff description: the contents of register f is moved to a destination dependant upon the sta- tus of d. if d = 0, destination is w reg- ister. if d = 1, the destination is ?e register f itself. d = 1 is useful to test a ?e register since status ?g z is affected. words: 1 cycles: 1 example movf fsr, 0 after instruction w = value in fsr register z= 1 movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) ? (f) status affected: none encoding: 00 0000 1fff ffff description: move data from w register to register 'f' . words: 1 cycles: 1 example movwf option before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f
1995 microchip technology inc. ds30390b-page 149 pic16c7x nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00 0000 0xx0 0000 description: no operation. words: 1 cycles: 1 example nop option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none encoding: 00 0000 0110 0010 description: the contents of the w register are loaded in the option register. this instruction is supported for code com- patibility with pic16c5x products. since option is a readable/writable register, the user can directly address it. words: 1 cycles: 1 example to maintain upward compatibility with future pic16cxx products, do not use this instruction. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none encoding: 00 0000 0000 1001 description: return from interrupt. stack is poped and top of stack (tos) is loaded in the pc. interrupts are enabled by set- ting global interrupt enable bit, gie (intcon<7>). this is a two cycle instruction. words: 1 cycles: 2 example retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k ? (w); tos ? pc status affected: none encoding: 11 01xx kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. words: 1 cycles: 2 example table call table ;w contains table ;offset value ? ;w now has table value addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8
pic16c7x ds30390b-page 150 1995 microchip technology inc. return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none encoding: 00 0000 0000 1000 description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two cycle instruction. words: 1 cycles: 2 example return after interrupt pc = tos rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1101 dfff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example rlf reg1,0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 = 1110 0110 w = 1100 1100 c =1 register f c rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1100 dfff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example rrf reg1,0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 = 1110 0110 w = 0111 0011 c =0 sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? t o , 0 ? pd status affected: t o , pd encoding: 00 0000 0110 0011 description: the power-down status bit, p d is cleared. time-out status bit, t o is set. watchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 14.8 for more details. words: 1 cycles: 1 example: sleep register f c
1995 microchip technology inc. ds30390b-page 151 pic16c7x sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ? ( w) status affected: c, dc, z encoding: 11 110x kkkk kkkk description: the w register is subtracted (2s com- plement method) from the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example 1: sublw 0x02 before instruction w= 1 c= ? after instruction w= 1 c = 1; result is positive example 2: before instruction w= 2 c= ? after instruction w= 0 c = 1; result is zero example 3: before instruction w= 3 c= ? after instruction w = 0xff c = 0; result is nega- tive subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d ? [0,1] operation: (f) - (w) ? ( dest) status affected: c, dc, z encoding: 00 0010 dfff ffff description: subtract (2s complement method) w reg- ister from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example 1: subwf reg1,1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1; result is positive example 2: before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1; result is zero example 3: before instruction reg1 = 1 w=2 c=? after instruction reg1 = 0xff w=2 c = 0; result is negative
pic16c7x ds30390b-page 152 1995 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d ? [0,1] operation: (f<3:0>) ? (dest<7:4>), (f<7:4>) ? (dest<3:0>) status affected: none encoding: 00 1110 dfff ffff description: the upper and lower nibbles of regis- ter 'f' are exchanged. if 'd' is 0 the result is placed in w register. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 example swapf reg, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: 5 f 7 operation: (w) ? tris register f; status affected: none encoding: 00 0000 0110 0fff description: the instruction is supported for code compatibility with the pic16c5x prod- ucts. since tris registers are read- able and writable, the user can directly address them. words: 1 cycles: 1 example to maintain upward compatibility with future pic16cxx products, do not use this instruction. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ? ( w) status affected: z encoding: 11 1010 kkkk kkkk description: the contents of the w register are xor?d with the eight bit literal 'k'. the result is placed in the w regis- ter. words: 1 cycles: 1 example: xorlw 0xaf before instruction w = 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .xor. (f) ? ( dest) status affected: z encoding: 00 0110 dfff ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg 1 before instruction reg = 0xaf w = 0xb5 after instruction reg = 0x1a w = 0xb5
1995 microchip technology inc. ds30390b-page 153 pic16c7x 16.0 development support 16.1 de velopme nt t ools the pic16/17 microcontrollers are supported with a full range of hardware and software development tools: picmaster ? real-time in-circuit emulator pro mate ? universal programmer picstart ? low-cost prototype programmer picdem-1 low-cost demonstration board picdem-2 low-cost demonstration board mpasm assembler mpsim software simulator c compiler (mp-c) fuzzy logic development system (fuzzytech - mp) 16.2 picmaster: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the picmaster universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the pic16c5x, pic16cxx and pic17cxx families. picmaster is supplied with the mplab ? integrated development environment (ide), which allows editing, "make" and download, and source debugging from a single environment. a picmaster system con?uration is shown in figure 16-1. interchangeable target probes allow the system to be easily recon?ured for emulation of different proces- sors. the universal architecture of the picmaster allows expansion to support all new pic16c5x, pic16cxx and pic17cxx microcontrollers. the picmaster emulator system has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. the pc compatible 386 (and better) machine platform and microsoft win- dows ? 3.x environment was chosen to best make these features available to you, the end user. the picmaster universal emulator system consists primarily of four major components: host-interface card emulator control pod target-speci? emulator probe pc-host emulation control software the windows operating system allows the developer to take full advantage of the many powerful features and functions of the picmaster system. picmaster emulation can operate in one window, while a text editor is running in a second window. pc-host emulation control software takes full advan- tage of dynamic data exchange (dde), a feature of windows. dde allows data to be dynamically trans- ferred between two or more windows programs. with this feature, data collected with picmaster can be automatically transferred to a spreadsheet or database program for further analysis. under windows, as many as four picmaster emula- tors can be run simultaneously from the same pc mak- ing development of multi-microcontroller systems possible (e.g., a system containing a pic16cxx pro- cessor and a pic17cxx processor). the picmaster probes speci?ations are shown in table 16-1. figure 16-1: picmaster system configuration windows 3.x common interface card pc compatible computer power switch power connector pc-interface in-line power supply (optional) 5 vdc picmaster emulator pod interchangeable emulator probe pc bus 90 - 250 vac logic probes this document was created with framemake r404
pic16c7x ds30390b-page 154 1995 microchip technology inc. table 16-1: picmaster probe specification devices picmaster probe probe maximum frequency operating voltage pic16c54 probe-16d 20 mhz 4.5v - 5.5v pic16c54a probe-16d 20 mhz 4.5v - 5.5v pic16cr54 probe-16d 20 mhz 4.5v - 5.5v pic16cr54a probe-16d (1) 20 mhz 4.5v - 5.5v pic16cr54b probe-16d (1) 20 mhz 4.5v - 5.5v pic16c55 probe-16d 20 mhz 4.5v - 5.5v pic16cr55 probe-16d (1) 20 mhz 4.5v - 5.5v pic16c56 probe-16d 20 mhz 4.5v - 5.5v pic16cr56 probe-16d (1) 20 mhz 4.5v - 5.5v pic16c57 probe-16d 20 mhz 4.5v - 5.5v pic16cr57a probe-16d 20 mhz 4.5v - 5.5v pic16cr57b probe-16d (1) 20 mhz 4.5v - 5.5v pic16c58a probe-16d 20 mhz 4.5v - 5.5v pic16cr58a probe-16d 20 mhz 4.5v - 5.5v pic16cr58b probe-16d (1) 20 mhz 4.5v - 5.5v pic16c61 probe-16g 10 mhz 4.5v - 5.5v pic16c62 probe-16e 10 mhz 4.5v - 5.5v pic16c62a probe-16e (1) 10 mhz 4.5v - 5.5v pic16cr62 probe-16e (1) 10 mhz 4.5v - 5.5v pic16c63 probe-16f (1) 10 mhz 4.5v - 5.5v pic16c64 probe-16e 10 mhz 4.5v - 5.5v pic16c64a probe-16e (1) 10 mhz 4.5v - 5.5v pic16cr64 probe-16e (1) 10 mhz 4.5v - 5.5v pic16c65 probe-16f 10 mhz 4.5v - 5.5v pic16c65a probe-16f (1) 10 mhz 4.5v - 5.5v pic16c620 probe-16h 10 mhz 4.5v - 5.5v pic16c621 probe-16h 10 mhz 4.5v - 5.5v pic16c622 probe-16h 10 mhz 4.5v - 5.5v PIC16C70 probe-16b (1) 10 mhz 4.5v - 5.5v pic16c71 probe-16b 10 mhz 4.5v - 5.5v pic16c71a probe-16b (1) 10 mhz 4.5v - 5.5v pic16c72 probe-16f (1) 10 mhz 4.5v - 5.5v pic16c73 probe-16f 10 mhz 4.5v - 5.5v pic16c73a probe-16f (1) 10 mhz 4.5v - 5.5v pic16c74 probe-16f 10 mhz 4.5v - 5.5v pic16c74a probe-16f (1) 10 mhz 4.5v - 5.5v pic16c83 probe-16c 10 mhz 4.5v - 5.5v pic16c84 probe-16c 10 mhz 4.5v - 5.5v pic17c42 probe-17b 20 mhz 4.5v - 5.5v pic17c43 probe-17b 20 mhz 4.5v - 5.5v pic17c44 probe-17b 20 mhz 4.5v - 5.5v note 1: this picmaster probe can be used to functionally emulate the device listed in the previous column. contact your microchip sales of?e for details. table 16-1: picmaster probe specification (cont.d) devices picmaster probe probe maximum frequency operating voltage
1995 microchip technology inc. ds30390b-page 155 pic16c7x 16.3 pr o ma te: univer sal pr ogrammer the pro mate universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. the pro mate has programmable v dd and v pp sup- plies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate can read, verify or program pic16c5x, pic16cxx and pic17cxx devices. it can also set con?uration and code-protect bits in this mode. in pc-hosted mode, the pro mate connects to the pc via one of the com (rs-232) ports. pc based user- interface software makes using the programmer simple and ef?ient. the user interface is full-screen and menu-based. full screen display and editing of data, easy selection of bit con?uration and part type, easy selection of v dd min, v dd max and v pp levels, load and store to and from disk ?es (intel a hex format) are some of the features of the software. essential commands such as read, verify, program and blank check can be issued from the screen. additionally, serial program- ming support is possible where each part is pro- grammed with a different serial number, sequential or random. the pro mate has a modular ?rogramming socket module? different socket modules are required for dif- ferent processor types and/or package types. pro mate supports all pic16c5x, pic16cxx and pic17cxx processors. 16.4 picst ar t lo w-cost de velopment system the picstart programmer is an easy to use, very low-cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. a pc-based user interface software makes using the programmer simple and ef?ient. the user interface is full-screen and menu-based. picstart is not recommended for pro- duction programming. 16.5 picdem-1 lo w-cost pic16/17 demonstration boar d the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample micro controllers provided with the picdem-1 board, on a pro mate or picstart-16b programmer, and easily test ?m- ware. the user can also connect the picdem-1 board to the picmaster emulator and down load the ?mware to the emulator for testing. additional pro- totype area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 16.6 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate pro- grammer or picstart-16c, and easily test ?mware. the picmaster emulator may also be used with the picdem-2 board to test ?mware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad.
pic16c7x ds30390b-page 156 1995 microchip technology inc. 16.7 mplab tm integrated de velopment en vir onment software . the mplab software brings an ease of software devel- opment previously unseen in the 8-bit microcontroller market. mplab is a windows based application which contains: a full featured editor three operating modes - editor - emulator - simulator (available soon) a project manager customizable tool bar and key mapping a status bar with project information extensive on-line help mplab allows you to: edit your source ?es (either assembly or "c") one touch assemble (or compile) and download to pic16/17 tools (automatically updates all project information) debug using: - source ?es - absolute listing ?e transfer data dynamically via dde (soon to be replaced by ole) run up to four emulators on the same pc the ability to use mplab with microchips simulator (available soon) allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 16.8 assemb ler (mp asm) the mpasm cross assembler is a pc-hosted symbolic assembler. it supports all microcontroller series includ- ing the pic16c5x, pic16cxx and pic17cxx families. mpasm offers full featured macro capabilities, condi- tional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers. mpasm allows full symbolic debugging from the micro chip universal emulator system (picmaster). mpasm has the following features to assist in develop- ing software for speci? use applications. provides translation of assembler source code to object code for all microchip microcontrollers. macro assembly capability. produces all the ?es (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the pic16/17. directives are helpful in making the development of your assemble source code shorter and more maintainable. data directives are those that control the alloca- tion of memory and provide a way to refer to data items symbolically, i.e., by meaningful names. control directives control the mpasm listing dis- play. they allow the speci?ation of titles and sub- titles, page ejects and other listing control. this eases the readability of the printed output ?e. conditional directives permit sections of condi- tionally assembled code. this is most useful where additional functionality may wished to be added depending on the product (less functional- ity for the low end product, then for the high end product). also this is very helpful in the debugging of a program. macro directives control the execution and data allocation within macro body de?itions. this makes very simple the re-use of functions in a program as well as between programs.
1995 microchip technology inc. ds30390b-page 157 pic16c7x 16.9 software sim ulator (mpsim) the mpsim software simulator allows code develop- ment in a pc host environment. it allows the user to simulate the pic16/17 series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mpsim fully supports symbolic debugging using mp-c and mpasm. the software simulator offers the low cost ?xibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 16.10 c compiler ( mp-c) the mp-c code development system is a complete 'c' compiler and integrated development environment for microchips pic16/17 family of microcontrollers. the compiler provides powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the picmaster universal emulator memory display (picmaster emulator software versions 1.13 and later). the mp-c code development system is supplied directly by byte craft limited of waterloo, ontario, canada. if you have any questions, please contact your regional microchip fae or microchip technical support personnel at (602) 786-7627. 16.11 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzytech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzytech-mp, edition for imple- menting more complex systems. both versions include microchips fuzzylab ? demon- stration board for hands-on experience with fuzzy logic systems implementation. 16.12 de velopment systems for convenience, the development tools are packaged into comprehensive systems as listed in table 16-2. table 16-2: development system packages item name system description 1. picmaster system picmaster in-circuit emulator, pro mate programmer, assembler, soft- ware simulator, samples and your choice of target probe. 2. picstart system picstart low-cost prototype programmer, assembler, software simulator and samples. 3. pro mate system pro mate universal programmer, full featured stand-alone or pc-hosted pro- grammer, assembler, simulator
pic16c7x ds30390b-page 158 1995 microchip technology inc. notes:
1995 microchip technology inc. preliminary ds30390b-page 159 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 17.0 electrical characteristics for PIC16C70 and pic16c71a absolute maximum ratings ? ambient temperature under bias................................................................................................................ .-55 to +125?c storage temperature .............................................................................................................................. -65?c to +150?c voltage on any pin with respect to v ss (except v dd and mclr ) ................................................... -0.6v to (v dd + 0.6v) voltage on v dd with respect to v ss ................................................................................................................ 0 to +7.5v voltage on mclr with respect to v ss (note 2) .................................................................................................0 to +14v total power dissipation (note 1)................................................................................................................................1.0w maximum current out of v ss pin ...........................................................................................................................300 ma maximum current into v dd pin ..............................................................................................................................250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..........................................................................................................25 ma maximum output current sourced by any i/o pin ....................................................................................................25 ma maximum current sunk by porta ........................................................................................................................200 ma maximum current sourced by porta...................................................................................................................200 ma maximum current sunk by portb........................................................................................................................200 ma maximum current sourced by portb ..................................................................................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd - v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow?level to the mclr pin rather than pulling this pin directly to v ss . ? notice: stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. this document was created with framemake r404
pic16c7x ds30390b-page 160 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a table 17-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) osc PIC16C70-04 pic16c71a-04 PIC16C70-10 pic16c71a-10 PIC16C70-20 pic16c71a-20 pic16lc70-04 pic16lc71a-04 jw devices rc v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 2.0 ma typ. at 3.0v i pd : 0.9 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 2.0 ma typ. at 3.0v i pd : 0.9 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v do not use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 10 mhz max. freq: 20 mhz max. freq: 10 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. do not use in lp mode do not use in lp mode v dd : 3.0v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v freq: 200 khz max. v dd : 3.0v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recommended that the user select the device type that ensures the speci?ations required.
1995 microchip technology inc. preliminary ds30390b-page 161 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 17.1 dc characteristics: PIC16C70-04 (commercial, industrial, automotive (5) ) pic16c71a-04 (commercial, industrial, automotive (5) ) PIC16C70-10 (commercial, industrial, automotive (5) ) pic16c71a-10 (commercial, industrial, automotive (5) ) PIC16C70-20 (commercial, industrial, automotive (5) ) pic16c71a-20 (commercial, industrial, automotive (5) ) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param. no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002 ram data retention voltage (note 1) v dr - 1.5* - v device in sleep mode d003 v dd start voltage to ensure power-on reset v por -v ss - v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05* - - v/ms see section on power-on reset for details d010 d013 supply current (note 2) i dd - - 2.7 13.5 5 30 ma ma xt, rc osc con?uration (PIC16C70/71a-04) f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con?uration (PIC16C70/71a-20) f osc = 20 mhz, v dd = 5.5v d015 brown-out reset cur- rent (note 6) d i bor - 300* 500 m a bor enabled v dd = 5.0v d020 d021 d021a d021b power-down current (note 3) i pd - - - - 10.5 1.5 1.5 1.5 42 21 24 tbd m a m a m a m a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -0 c to +70 c v dd = 4.0v, wdt disabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -40 c to +125 c d023 brown-out reset cur- rent (note 6) d i bor - 300* 500 m a bor enabled v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: automotive operating range is advanced information for this device. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
pic16c7x ds30390b-page 162 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a 17.2 dc characteristics: pic16lc70-04 (commercial, industrial, automotive (5) ) pic16lc71a-04 (commercial, industrial, automotive (5) ) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 3.0 - 6.0 v lp, xt, rc osc con?uration (dc - 4 mhz) d002 ram data retention voltage (note 1) v dr - 1.5* - v device in sleep mode d003 v dd start voltage to ensure power-on reset v por -v ss - v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05* - - v/ms see section on power-on reset for details d010 d010a supply current (note 2,5) i dd - - 2.0 22.5 3.8 48 ma m a xt, rc osc con?uration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con?uration f osc = 32 khz, v dd = 3.0v, wdt disabled d015 brown-out reset cur- rent (note 6) d i bor - 300* 500 m a bor enabled v dd = 3.0v d020 d021 d021a d021b power-down current (note 3,5) i pd - - - - 7.5 0.9 0.9 0.9 30 5 5 10 m a m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c v dd = 3.0v, wdt disabled, -40 c to +125 c d023 brown-out reset cur- rent (note 6) d i bor - 300* 500 m a bor enabled v dd = 3.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: automotive operating range is advanced information for this device. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
1995 microchip technology inc. preliminary ds30390b-page 163 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 17.3 dc characteristics: PIC16C70-04 (commercial, industrial, automotive (4) ) pic16c71a-04 (commercial, industrial, automotive (4) ) PIC16C70-10 (commercial, industrial, automotive (4) ) pic16c71a-10 (commercial, industrial, automotive (4) ) PIC16C70-20 (commercial, industrial, automotive (4) ) pic16c71a-20 (commercial, industrial, automotive (4) ) pic16lc70-04 (commercial, industrial, automotive (4) ) pic16lc71a-04 (commercial, industrial, automotive (4) ) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 17.1 and section 17.2. param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 with ttl buffer v ss - 0.5v v d031 with schmitt trigger buffer v ss - 0.2v dd v d032 mclr , ra4/t0cki,osc1 (in rc mode) v ss - 0.2v dd v d033 osc1 (in xt, hs and lp) v ss - 0.3v dd v note1 input high voltage i/o ports v ih - d040 with ttl buffer 2.0 - v dd v 4.5 v dd 5.5v d040a 0.8v dd -v dd v for v dd > 5.5v or v dd < 4.5v d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr , ra4/t0cki rb0/int 0.8v dd -v dd v d042a osc1 (xt, hs and lp) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 250 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc con?uration output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a - - 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: automotive operating range is advanced information for this device.
pic16c7x ds30390b-page 164 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a output high voltage d090 i/o ports (note 3) v oh v dd - 0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd - 0.7 - - v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc con?) v dd - 0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd - 0.7 - - v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c capacitive loading specs on out- put pins d100 osc2 pin c osc2 - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 all i/o pins and osc2 (in rc mode) c io - - 50 pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 17.1 and section 17.2. param no. characteristic sym min typ ? max units conditions ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: automotive operating range is advanced information for this device.
1995 microchip technology inc. preliminary ds30390b-page 165 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 17.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 17-1: load conditions 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2
pic16c7x ds30390b-page 166 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a 17.5 t iming dia grams and speci cations figure 17-2: external clock timing table 17-2: clock timing requirements parameter no. sym characteristic min typ? max units conditions fos external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (PIC16C70/71a-04,) dc 20 mhz hs osc mode (PIC16C70/71a-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 4 mhz hs osc mode (PIC16C70/71a-04) 4 4 5 10 20 200 mhz mhz khz hs osc mode (PIC16C70/71a-10) hs osc mode (PIC16C70/71a-20) lp osc mode 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (PIC16C70/71a-04) 100 ns hs osc mode (PIC16C70/71a-10) 50 ns hs osc mode (PIC16C70/71a-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (PIC16C70/71a-04) 100 50 250 250 ns ns hs osc mode (PIC16C70/71a-10) hs osc mode (PIC16C70/71a-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 dc ns t cy = 4/f osc 3 tosl, tosh external clock in (osc1) high or low time 50 ns xt oscillator 2.5 m s lp oscillator 10 ns hs oscillator 4 tosr, tosf external clock in (osc1) rise or fall time ? 25 ns xt oscillator ? 50 ns lp oscillator 15 ns hs oscillator ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. osc2 is disconnected (has no loading) for the PIC16C70/71a. osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
1995 microchip technology inc. preliminary ds30390b-page 167 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 17-3: clkout and i/o timing table 17-3: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 15 30 ns note 1 11* tosh2ckh osc1 - to clkout - 15 30 ns note 1 12* tckr clkout rise time 5 15 ns note 1 13* tckf clkout fall time 5 15 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - 0.25t cy + 25 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 80 - 100 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) tbd ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) tbd ns 20* tior port output rise time PIC16C70/71a 10 25 ns pic16lc70/71a 60 ns 21* tiof port output fall time PIC16C70/71a 10 25 ns pic16lc70/71a 60 ns 22??* tinp int pin high or low time 20 ns 23??* trbp rb7:rb4 change int high or low time 20 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 17-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16c7x ds30390b-page 168 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 17-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 17-5: brown-out reset timing table 17-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 1 m sv dd = 5v, -40?c to +125?c 31 twdt watchdog timer time-out period (no prescaler) 7* 18 33* ms v dd = 5v, -40?c to +125?c 32 tost oscillation start-up timer period 1024t osc t osc = osc1 period 33 tpwrt power up timer period 28* 72 132* ms v dd = 5v, -40?c to +125?c 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset 1.1 m s 35 t bor brown-out reset pulse width 100 m s 3.8v v dd 4.2v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 17-1 for load conditions. v dd bv dd 35
1995 microchip technology inc. preliminary ds30390b-page 169 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 17-6: timer0 clock timings table 17-5: timer0 clock requirements param no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20* ns with prescaler 10* ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20* ns with prescaler 10* ns 42 tt0p t0cki period greater of: 20 m s or t cy + 40 * n ns n = prescale value (1, 2, 4,..., 256) 48 tcke2tmri delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 17-1 for load conditions. 41 42 40 ra4/t0cki tmr0
pic16c7x ds30390b-page 170 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a table 17-6: a/d converter characteristics: PIC16C70-04 (commercial, industrial, automotive (3) ) pic16c71a-04 (commercial, industrial, automotive (3) ) PIC16C70-10 (commercial, industrial, automotive (3) ) pic16c71a-10 (commercial, industrial, automotive (3) ) PIC16C70-20 (commercial, industrial, automotive (3) ) pic16c71a-20 (commercial, industrial, automotive (3) ) parameter no. sym characteristic min typ? max units conditions n r resolution 8-bits v ref = v dd = 5.12v, v ss a in v ref n int integral error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n dif differential error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n fs full scale error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n off offset error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref monotonicity guaranteed v ss a in v ref v ref reference voltage 3.0v v dd + 0.3 v v ain analog input voltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of analog voltage source 10.0 k w i ad a/d conversion cur- rent (v dd ) 180 m a average current consumption when a/d is on. (note 1) i ref v ref input current (note 2) 1 10 ma m a during sampling all other times * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 3: automotive operating range is advanced information for this device.
1995 microchip technology inc. preliminary ds30390b-page 171 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a table 17-7: a/d converter characteristics: pic16lc70-04 (commercial, industrial, automotive (4) ) pic16lc71a-04 (commercial, industrial, automotive (4) ) parameter no. sym characteristic min typ? max units conditions n r resolution 8-bits v ref = v dd = 3.0v (note 1) n int integral error less than 1 lsb ? ref = v dd = 3.0v (note 1) n dif differential error less than 1 lsb ? ref = v dd = 3.0v (note 1) n fs full scale error less than 1 lsb ? ref = v dd = 3.0v (note 1) n off offset error less than 1 lsb ? ref = v dd = 3.0v (note 1) monotonicity guaranteed v ss a in v ref v ref reference voltage 3.0v v dd + 0.3 v v ain analog input voltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of ana- log voltage source 10.0 k w i ad a/d conversion cur- rent (v dd ) ?0 m a average current consumption when a/d is on. (note 2) i ref v ref input current (note 3) 1 10 ma m a during sampling all other times * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: these speci?ations apply if v ref = 3.0v and if v dd 3 3.0v. v in must be between v ss and v ref 2: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 3: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 4: automotive operating range is advanced information for this device.
pic16c7x ds30390b-page 172 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 17-7: a/d conversion timing table 17-8: a/d conversion requirements parameter no. sym characteristic min typ? max units conditions 130 t ad a/d clock period 1.6 2.0 m s m s v ref 3 3.0v v ref full range 130 t ad a/d internal rc oscillator source adcs1:adcs0 = 11 (rc oscillator source) 3.0 6.0 9.0 m s pic16lc70, v dd = 3.0v 2.0 4.0 6.0 m s PIC16C70 131 t cnv conversion time (not including s/h time). note 1 9.5t ad 132 t smp sampling time note 2 20 m s * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 13.1 for min conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 tcy
1995 microchip technology inc. preliminary ds30390b-page 173 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 18.0 dc and ac characteristics graphs and tables for PIC16C70 and pic16c71a not available at this time this document was created with framemake r404
pic16c7x ds30390b-page 174 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a notes:
1995 microchip technology inc. ds30390b-page 175 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 19.0 electrical characteristics for pic16c71 absolute maximum ratings ? ambient temperature under bias................................................................................................................ .-55 to +125?c storage temperature .............................................................................................................................. -65?c to +150?c voltage on any pin with respect to v ss (except v dd and mclr ) ................................................... -0.6v to (v dd + 0.6v) voltage on v dd with respect to v ss ................................................................................................................ 0 to +7.5v voltage on mclr with respect to v ss (note 2) .................................................................................................0 to +14v total power dissipation (note 1)...........................................................................................................................800 mw maximum current out of v ss pin ...........................................................................................................................150 ma maximum current into v dd pin ..............................................................................................................................100 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..........................................................................................................25 ma maximum output current sourced by any i/o pin ....................................................................................................20 ma maximum current sunk by porta ..........................................................................................................................80 ma maximum current sourced by porta.....................................................................................................................50 ma maximum current sunk by portb........................................................................................................................150 ma maximum current sourced by portb ..................................................................................................................100 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow?level to the mclr pin rather than pulling this pin directly to v ss . table 19-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ? notice: stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. osc pic16c71-04 pic16c71-20 pic16lc71-04 jw devices rc v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 1.8 ma typ. at 5.5v i pd : 1.0 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 1.4 ma typ. at 3.0v i pd : 0.6 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 1.8 ma typ. at 5.5v i pd : 1.0 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 1.4 ma typ. at 3.0v i pd : 0.6 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 3.3 ma max. at 5.5v i pd : 14 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v do not use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i pd : 1.0 m a typ. at 4.5v i pd : 1.0 m a typ. at 4.5v i pd : 1.0 m a typ. at 4.5v freq: 4 mhz max. freq: 20 mhz max. freq: 20 mhz max. lp v dd : 4.0v to 6.0v i dd : 15 m a typ. at 32 khz, 4.0v i pd : 0.6 m a typ. at 4.0v freq: 200 khz max. do not use in lp mode v dd : 3.0v to 6.0v i dd : 32 m a max. at 32 khz, 3.0v i pd : 9 m a max. at 3.0v freq: 200 khz max. v dd : 3.0v to 6.0v i dd : 32 m a max. at 32 khz, 3.0v i pd : 9 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recom- mended that the user select the device type that ensures the speci?ations required. this document was created with framemake r404
pic16c7x ds30390b-page 176 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a 19.1 dc characteristics: pic16c71-04 (commercial, industrial) pic16c71-20 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002 ram data retention voltage (note 1) v dr - 1.5* - v device in sleep mode d003 v dd start voltage to guarantee power-on reset v po r -v ss - v see section on power-on reset for details d004 v dd rise rate to guarantee power-on reset s vd d 0.05* - - v/ms see section on power-on reset for details d010 d013 supply current (note 2) i dd - - 1.8 13.5 3.3 30 ma ma f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con?uration (pic16c71-20) f osc = 20 mhz, v dd = 5.5v d020 d021 d021a power-down current (note 3) i pd - - - 7 1.0 1.0 28 14 16 m a m a m a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -0 c to +70 c v dd = 4.0v, wdt disabled, -40 c to +85 c * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm.
1995 microchip technology inc. ds30390b-page 177 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 19.2 dc characteristics: pic16lc71-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 3.0 - 6.0 v xt, rc, and lp osc con?uration d002 ram data retention voltage (note 1) v dr - 1.5* - v device in sleep mode d003 v dd start voltage to ensure power-on reset v por -v ss - v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05* - - v/ms see section on power-on reset for details d010 d010a supply current (note 2) i dd - - 1.4 15 2.5 32 ma m a f osc = 4 mhz, v dd = 3.0v (note 4) f osc = 32 khz, v dd = 3.0v, wdt disabled d020 d021 d021a power-down current (note 3) i pd - - - 5 0.6 0.6 20 9 12 m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm.
pic16c7x ds30390b-page 178 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a 19.3 dc characteristics: pic16c71-04 (commercial, industrial) pic16c71-20 (commercial, industrial) pic16lc71-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 19.1 and section 19.2. param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 with ttl buffer v ss - 0.5v v d031 with schmitt trigger buffer v ss - 0.2v dd v d032 mclr , ra4/t0cki,osc1 (in rc mode) v ss - 0.2v dd v d033 osc1 (in xt, hs and lp) v ss - 0.3v dd v note1 input high voltage i/o ports (note 4) v ih - d040 with ttl buffer 0.36v dd -v dd v 4.5 v dd 5.5v d040a 0.45v dd -v dd for v dd > 5.5v or v dd < 4.5v d041 with schmitt trigger buffer 0.85v dd -v dd for entire v dd range d042 mclr ra4/t0cki 0.85v dd -v dd v d042a osc1 (xt, hs and lp) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 250 ?400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc con?uration output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6ma, v dd = 4.5v, -40 c to +85 c output high voltage d090 i/o ports (note 3) v oh v dd - 0.7 - - v i oh = -3.0ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clkout (rc osc con?) v dd - 0.7 - - v i oh = -1.3ma, v dd = 4.5v, -40 c to +85 c ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1 pin is a schmitt trigger input. it is not recommended that the pic16c71 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: pic16c71 rev. "ax" int pin has a ttl input buffer. pic16c71 rev. "bx" int pin has a schmitt trigger input buffer.
1995 microchip technology inc. ds30390b-page 179 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a capacitive loading specs on out- put pins d100 osc2 pin c osc2 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 all i/o pins and osc2 (in rc mode) c io 50 pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 19.1 and section 19.2. param no. characteristic sym min typ ? max units conditions ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1 pin is a schmitt trigger input. it is not recommended that the pic16c71 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: pic16c71 rev. "ax" int pin has a ttl input buffer. pic16c71 rev. "bx" int pin has a schmitt trigger input buffer.
pic16c7x ds30390b-page 180 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a 19.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 19-1: load conditions 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2/clkout 15 pf for osc2 output load condition 1 load condition 2
1995 microchip technology inc. ds30390b-page 181 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 19.5 timing dia grams and speci cations figure 19-2: external clock timing table 19-2: external clock timing requirements parameter no. sym characteristic min typ? max units conditions fos external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (pic16c71-04) dc 20 mhz hs osc mode (pic16c71-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 1 4 mhz hs osc mode (pic16c71-04) 1 20 mhz hs osc mode (pic16c71-20) 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (pic16c71-04) 50 ns hs osc mode (pic16c71-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 1,000 ns hs osc mode (pic16c71-04) 50 1,000 ns hs osc mode (pic16c71-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 1.0 dc m s tcy = 4/fosc 3 tosl, tosh clock in (osc1) high or low time 50 ns xt oscillator 2.5 m s lp oscillator 10 ns hs oscillator 4 tosr, tosf clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. osc2 is disconnected (has no loading) for the pic16c71. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
pic16c7x ds30390b-page 182 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 19-3: clkout and i/o timing table 19-3: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 15 30 ns note 1 11* tosh2ckh osc1 - to clkout - 15 30 ns note 1 12* tckr clkout rise time 5 15 ns note 1 13* tckf clkout fall time 5 15 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - 0.25t cy + 25 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 80 - 100 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) tbd ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) tbd ns 20* tior port output rise time pic16c71 10 25 ns pic16lc71 60 ns 21* tiof port output fall time pic16c71 10 25 ns pic16lc71 60 ns 22??* tinp int pin high or low time 20 ns 23??* trbp rb7:rb4 change int high or low time 20 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 19-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
1995 microchip technology inc. ds30390b-page 183 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 19-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing table 19-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 200 ns v dd = 5v, -40?c to +85?c 31 twdt watchdog timer time-out period 7* 18 33* ms v dd = 5v, -40?c to +85?c (no prescaler) 32 tost oscillation start-up timer period 1024 t osc t osc = osc1 period 33 tpwrt power-up timer period 28* 72 132* ms v dd = 5v, -40?c to +85?c 34 t ioz i/o high impedance from mclr low 100 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 19-1 for load conditions.
pic16c7x ds30390b-page 184 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 19-5: timer0 clock timings table 19-5: timer0 clock requirements param no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20* ns with prescaler 10* ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20* ns with prescaler 10* ns 42 tt0p t0cki period greater of: 20 m s or t cy + 40 * n ns n = prescale value (2, 4,..., 256) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 19-1 for load conditions. 41 42 40 ra4/t0cki tmr0
1995 microchip technology inc. ds30390b-page 185 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a table 19-6: a/d converter characteristics: pic16c71-04 (commercial, industrial) pic16c71-20 (commercial, industrial) parameter no. sym characteristic min typ? max units conditions n r resolution 8 bits v ref = v dd = 5.12v, v ss a in v ref n int integral error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n dif differential error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n fs full scale error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n off offset error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref monotonicity guaranteed v ss a in v ref v ref reference voltage 3.0v v dd + 0.3 v v ain analog input voltage v ss - 0.3 v ref v z ain recommended impedance of analog voltage source 10.0 k w i ad a/d conversion cur- rent (v dd ) 180 m a average current consumption when a/d is on. (note 1) i ref v ref input current (note 2) 1 40 ma m a during sampling all other times * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input.
pic16c7x ds30390b-page 186 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a table 19-7: a/d converter characteristics: pic16lc71-04 (commercial, industrial) parameter no. sym characteristic min typ? max units conditions n r resolution 8 bits v ref = v dd = 3.0v (note 1) n int integral error less than 2 lsb ? ref = v dd = 3.0v (note 1) n dif differential error less than 2 lsb ? ref = v dd = 3.0v (note 1) n fs full scale error less than 2 lsb ? ref = v dd = 3.0v (note 1) n off offset error less than 2 lsb ? ref = v dd = 3.0v (note 1) monotonicity guaranteed v ss a in v ref v ref reference voltage 3.0v v dd + 0.3 v v ain analog input voltage v ss - 0.3 v ref v z ain recommended impedance of ana- log voltage source 10.0 k w i ad a/d conversion cur- rent (v dd ) ?0 m a average current consumption when a/d is on. (note 2) i ref v ref input current (note 3) 1 10 ma m a during sampling all other times * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: these speci?ations apply if v ref = 3.0v and if v dd 3 3.0v. v in must be between v ss and v ref 2: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 3: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input.
1995 microchip technology inc. ds30390b-page 187 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 19-6: a/d conversion timing table 19-8: a/d conversion requirements parameter no. sym characteristic min typ? max units conditions 130 t ad a/d clock period 2.0 m s 130 t ad a/d internal rc oscillator source adcs1:adcs0 = 11 (rc oscillator source) 3.0 6.0 9.0 m s pic16lc71, v dd = 3.0v 2.0 4.0 6.0 m s pic16c71 131 t cnv conversion time (not including s/h time) (note 1) 10t ad 132 t smp sampling time note 2 20 m s * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 13.1 for min conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 tcy
pic16c7x ds30390b-page 188 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30390b-page 189 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 20.0 dc and ac characteristics graphs and tables for pic16c71 the graphs and tables provided in this section are for design guidance and are not tested or guaranteed. in some graphs or tables the data presented are out- side speci?d operating range (e.g. outside speci- ?d v dd range). this is for information only and devices are guaranteed to operate properly only within the speci?d range. the data presented in this section is a statistical sum- mary of data collected on units from different lots over a period of time. 'typical' represents the mean of the distribution while 'max' or 'min' represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard devi- ation. figure 20-1: typical rc oscillator frequency vs. temperature frequency normalized to 25 c 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 fosc fosc (25 c) t( c) rext = 10k cext = 100 pf v dd = 5.5v v dd = 3.5v 0 1020 3040506070 figure 20-2: typical rc oscillator frequency vs. v dd figure 20-3: typical rc oscillator frequency vs. v dd 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) fosc (mhz) r = 4.7k r = 10k r = 100k cext = 20 pf, t = 25 c 2.0 1.8 1.0 0.8 0.6 0.4 0.2 0.0 3.0 4.0 3.5 4.5 5.0 5.5 6.0 v dd (volts) fosc (mhz) r = 3.3k r = 4.7k r = 10k cext = 100 pf, t = 25 c r = 100k 1.6 1.4 1.2 this document was created with framemake r404
pic16c7x ds30390b-page 190 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 20-4: typical rc oscillator frequency vs. v dd figure 20-5: typical i pd vs. v dd watchdog timer disabled 25 c 0.0 3.0 v dd (volts) fosc (mhz) cext = 300 pf, t = 25 c r = 100k 3.5 4.0 4.5 5.0 5.5 6.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 r = 10k r = 4.7k r = 3.3k 0.0 3.0 v dd (volts) i pd ( m a) 0.1 0.2 0.3 0.4 0.5 0.6 3.5 4.0 4.5 5.0 5.5 6.0 table 20-1: rc oscillator frequencies the percentage variation indicated here is part to part variation due to normal process distribution. the varia- tion indicated is 3 standard deviation from average value for v dd = 5v. figure 20-6: typical i pd vs. v dd watchdog timer enabled 25 c cext rext average f osc @ 5v, 25 c 20 pf 4.7k 10k 100k 4.52 mhz 2.47 mhz 290.86 khz 17.35% 10.10% 11.90% 100 pf 3.3k 4.7k 10k 100k 1.92 mhz 1.49 mhz 788.77 khz 88.11 khz 9.43% 9.83% 10.92% 16.03% 300 pf 3.3k 4.7k 10k 100k 726.89 khz 573.95 khz 307.31 khz 33.82 khz 10.97% 10.14% 10.43% 11.24% v dd (volts) i pd ( m a) 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2 4 6 8 10 12 14
1995 microchip technology inc. ds30390b-page 191 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 20-7: maximum i pd vs. v dd watchdog disabled 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) 0 c -55 c -40 c 70 c 85 c 125 c i pd ( m a) 25 20 15 10 5 0 figure 20-8: maximum i pd vs. v dd watchdog enabled i pd , with watchdog timer enabled, has two components: the leakage current which increases with higher tempera- ture and the operating current of the watchdog timer logic which increases with lower temperature. at -40 c, the latter dominates explaining the apparently anomalous behavior. 0 c -55 c -40 c 70 c 85 c 125 c 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) i pd ( m a) 45 40 35 30 25 20 15 10 5 0 figure 20-9: v th (input threshold voltage) of i/o pins vs. v dd v dd (volts) 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 25?c, typ min (-40?c to 85?c) 0.60 max (-40?c to 85?c) v th (volts)
pic16c7x ds30390b-page 192 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 20-10: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd figure 20-11: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) note: these input pins have a schmitt trigger input buffer. v ih , v il (volts) v ih , max (-40 c to 85 c) v ih , typ (25 c) v ih , min (-40 c to 85 c) v il , max (-40 c to 85 c) v il , typ (25 c) v il , min (-40 c to 85 c) 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v dd (volts) v th (volts) min (-40 c to 85 c) max (-40 c to 85 c) min (-40 c to 85 c) t yp (25 c)
1995 microchip technology inc. ds30390b-page 193 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 20-12: typical i dd vs. freq (ext clock, 25 c) figure 20-13: maximum, i dd vs. freq (ext clock, -40 to +85 c) 1 10 100 1,000 10,000 10,000 100,000 1,000,000 10,000,000 100,000,000 i dd ( m a) frequency (hz) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 10 100 1,000 10,000 10,000 100,000 1,000,000 10,000,000 100,000,000 i dd ( m a) frequency (hz) 6.0 5.5 5.0 4.5 4.0 3.5 3.0
pic16c7x ds30390b-page 194 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 20-14: maximum i dd vs. freq with a/d off (ext clock, -55 to +125 c) 10 100 1,000 10,000 10,000 100,000 1,000,000 10,000,000 100,000,000 i dd ( m a) frequency (hz) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 figure 20-15: wdt timer time-out period vs. v dd 50 45 40 35 30 25 20 15 10 5 234567 v dd (volts) wdt period (ms) max, 85 c max, 70 c typ, 25 c min, 0 c min, -40 c figure 20-16: transconductance (gm) of hs oscillator vs. v dd min, 85 c typ, 25 c max, -40 c 234567 v dd (volts) gm ( m a/v) 0 9000 8000 7000 6000 5000 4000 3000 2000 1000
1995 microchip technology inc. ds30390b-page 195 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 20-17: transconductance (gm) of lp oscillator vs. v dd figure 20-18: transconductance (gm) of xt oscillator vs. v dd min, 85 c typ, 25 c max, -40 c 225 200 175 150 125 100 75 50 25 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) gm ( m a/v) min, 85 c typ, 25 c max, -40 c 2 34 56 7 v dd (volts) 2500 2000 1500 1000 500 0 gm ( m a/v) figure 20-19: i oh vs. v oh , v dd = 3v figure 20-20: i oh vs. v oh , v dd = 5v min, 85 c typ, 25 c max, -40 c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v oh (volts) i oh (ma) 0 -5 -10 -15 -20 -25 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v oh (volts) i oh (ma) min @ 85 c typ @ 25 c max @ -40 c
pic16c7x ds30390b-page 196 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 20-21: i ol vs. v ol , v dd = 3v figure 20-22: i ol vs. v ol , v dd = 5v 35 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v ol (volts) i ol (ma) max @ -40 c typ @ 25 c min @ +85 c max @ -40 c 80 90 70 60 50 40 30 20 10 0 v ol (volts) i ol (ma) min @ +85 c typ @ 25 c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 table 20-2: input capacitance* pin name typical capacitance (pf) 18l pdip 18l soic ra port 5.0 4.3 rb port 5.0 4.3 mclr 17.0 17.0 osc1/clkn 4.0 3.5 osc2/clkout 4.3 3.5 tmr0 3.2 2.8 *all capacitance values are typical at 25 c. a part-to- part variation of 25% (three standard deviations) should be taken into account.
1995 microchip technology inc. preliminary ds30390b-page 197 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 21.0 electrical characteristics for pic16c72 absolute maximum ratings ? ambient temperature under bias................................................................................................................ .-55 to +125?c storage temperature .............................................................................................................................. -65?c to +150?c voltage on any pin with respect to v ss (except v dd and mclr ) ................................................... -0.6v to (v dd + 0.6v) voltage on v dd with respect to v ss ................................................................................................................ 0 to +7.5v voltage on mclr with respect to v ss (note 2) .................................................................................................0 to +14v total power dissipation (note 1)................................................................................................................................1.0w maximum current out of v ss pin ...........................................................................................................................300 ma maximum current into v dd pin ..............................................................................................................................250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..........................................................................................................25 ma maximum output current sourced by any i/o pin ....................................................................................................25 ma maximum current sunk by porta and portb (combined).................................................................................200 ma maximum current sourced by porta and portb (combined)............................................................................200 ma maximum current sunk by portc .......................................................................................................................200 ma maximum current sourced by portc ..................................................................................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd - v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow?level to the mclr pin rather than pulling this pin directly to v ss . ? notice: stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. this document was created with framemake r404
pic16c7x ds30390b-page 198 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a table 21-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) osc pic16c72-04 pic16c72-10 pic16c72-20 pic16lc72-04 jw devices rc v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 2.0 ma typ. at 3.0v i pd : 0.9 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 2.0 ma typ. at 3.0v i pd : 0.9 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v do not use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 10 mhz max. freq: 20 mhz max. freq: 10 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. do not use in lp mode do not use in lp mode v dd : 3.0v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v freq: 200 khz max. v dd : 3.0v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recommended that the user select the device type that ensures the speci?ations required.
1995 microchip technology inc. preliminary ds30390b-page 199 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 21.1 dc characteristics: pic16c72-04 (commercial, industrial, automotive (6) ) pic16c72-10 (commercial, industrial, automotive (6) ) pic16c72-20 (commercial, industrial, automotive (6) ) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002 ram data retention voltage (note 1) v dr - 1.5* - v device in sleep mode d003 v dd start voltage to ensure power-on reset v por -v ss - v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05* - - v/ms see section on power-on reset for details d010 d013 supply current (note 2,5) i dd - - 2.7 13.5 5 30 ma ma xt, rc osc con?uration (pic16c72-04) f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con?uration (pic16c72-20) f osc = 20 mhz, v dd = 5.5v d015 brown-out reset current (note 7) d i bor - 300* 500 m a bor enabled v dd = 5.0v d020 d021 d021a d021b power-down current (note 3,5) i pd - - - - 10.5 1.5 1.5 1.5 42 21 24 tbd m a m a m a m a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -0 c to +70 c v dd = 4.0v, wdt disabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -40 c to +125 c d023 brown-out reset current (note 7) d i bor - 300* 500 m a bor enabled v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from charac- terization and is for design guidance only. this is not tested. 6: automotive operating range is advanced information for this device. 7: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
pic16c7x ds30390b-page 200 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a 21.2 dc characteristics: pic16lc72-04 (commercial, industrial, automotive (6) ) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 3.0 - 6.0 v lp, xt, rc osc con?uration (dc - 4 mhz) d002 ram data retention voltage (note 1) v dr - 1.5* - v device in sleep mode d003 v dd start voltage to ensure power-on reset v por -v ss - v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05* - - v/ms see section on power-on reset for details d010 d010a supply current (note 2,5) i dd - - 2.0 22.5 3.8 48 ma m a xt, rc osc con?uration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con?uration f osc = 32 khz, v dd = 3.0v, wdt disabled d015 brown-out reset cur- rent (note 7) d i bor - 300* 500 m a bor enabled v dd = 3.0v d020 d021 d021a d021b power-down current (note 3,5) i pd - - - - 7.5 0.9 0.9 0.9 30 5 5 10 m a m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c v dd = 3.0v, wdt disabled, -40 c to +125 c d023 brown-out reset cur- rent (note 7) d i bor - 300* 500 m a bor enabled v dd = 3.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from charac- terization and is for design guidance only. this is not tested. 6: automotive operating range is advanced information for this device. 7: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
1995 microchip technology inc. preliminary ds30390b-page 201 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 21.3 dc characteristics: pic16c72-04 (commercial, industrial, automotive (4) ) pic16c72-10 (commercial, industrial, automotive (4) ) pic16c72-20 (commercial, industrial, automotive (4) ) pic16lc72-04 (commercial, industrial, automotive (4) ) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 21.1 and section 21.2. param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 with ttl buffer v ss - 0.5v v d031 with schmitt trigger buffer v ss - 0.2v dd v d032 mclr , ra4/t0cki,osc1 (in rc mode) v ss - 0.2v dd v d033 osc1 (in xt, hs and lp) v ss - 0.3v dd v note1 input high voltage i/o ports v ih - d040 with ttl buffer 2.0 - v dd v 4.5 v dd 5.5v d040a 0.8v dd -v dd v for v dd > 5.5v or v dd < 4.5v d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr , ra4/t0cki, rc7:rc4, rb0/ int 0.8v dd -v dd v d042a osc1 (xt, hs and lp) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 250 ?400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc con?uration output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a - - 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: automotive operating range is advanced information for this device.
pic16c7x ds30390b-page 202 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a output high voltage d090 i/o ports (note 3) v oh v dd - 0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd - 0.7 - - v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc con?) v dd - 0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd - 0.7 - - v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c capacitive loading specs on out- put pins d100 osc2 pin c osc2 - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 d102 all i/o pins and osc2 (in rc mode) scl, sda in i 2 c mode c io c b - - - - 50 400 pf pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 21.1 and section 21.2. param no. characteristic sym min typ ? max units conditions ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: automotive operating range is advanced information for this device.
1995 microchip technology inc. preliminary ds30390b-page 203 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 21.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 21-1: load conditions 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2
pic16c7x ds30390b-page 204 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a 21.5 t iming dia grams and speci cations figure 21-2: external clock timing table 21-2: clock timing requirements parameter no. sym characteristic min typ? max units conditions fos external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (pic16c72-04) dc 20 mhz hs osc mode (pic16c72-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 4 mhz hs osc mode (pic16c72-04) 4 4 5 10 20 200 mhz mhz khz hs osc mode (pic16c72-10) hs osc mode (pic16c72-20) lp osc mode 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (pic16c72-04) 100 ns hs osc mode (pic16c72-10) 50 ns hs osc mode (pic16c72-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (pic16c72-04) 100 50 250 250 ns ns hs osc mode (pic16c72-10) hs osc mode (pic16c72-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 dc ns t cy = 4/f osc 3 tosl, tosh external clock in (osc1) high or low time 50 ns xt oscillator 2.5 m s lp oscillator 10 ns hs oscillator 4 tosr, tosf external clock in (osc1) rise or fall time ? 25 ns xt oscillator ? 50 ns lp oscillator 15 ns hs oscillator ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
1995 microchip technology inc. preliminary ds30390b-page 205 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 21-3: clkout and i/o timing table 21-3: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 15 30 ns note 1 11* tosh2ckh osc1 - to clkout - 15 30 ns note 1 12* tckr clkout rise time 5 15 ns note 1 13* tckf clkout fall time 5 15 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - 0.25t cy + 25 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 80 - 100 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) tbd ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) tbd ns 20* tior port output rise time pic16c72 10 25 ns pic16lc72 60 ns 21* tiof port output fall time pic16c72 10 25 ns pic16lc72 60 ns 22??* tinp int pin high or low time 20 ns 23??* trbp rb7:rb4 change int high or low time 20 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 21-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16c7x ds30390b-page 206 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 21-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 21-5: brown-out reset timing table 21-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 1 m sv dd = 5v, -40?c to +125?c 31 twdt watchdog timer time-out period (no prescaler) 7* 18 33* ms v dd = 5v, -40?c to +125?c 32 tost oscillation start-up timer period 1024t osc t osc = osc1 period 33 tpwrt power-up timer period 28* 72 132* ms v dd = 5v, -40?c to +125?c 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset 1.1 m s 35 t bor brown-out reset pulse width 100 m s 3.8v v dd 4.2v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 21-1 for load conditions. v dd bv dd 35
1995 microchip technology inc. preliminary ds30390b-page 207 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 21-6: timer0 and timer1 clock timings table 21-5: timer0 and timer1 clock requirements param no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20* ns with prescaler 10* ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20* ns with prescaler 10* ns 42 tt0p t0cki period greater of: 20 m s or t cy + 40 * n ns n = prescale value (1, 2, 4, ..., 256) 45 tt1h t1cki high time synchronous, no prescaler 0.5tcy + 20 ns synchronous, with prescaler pic16c72 10* ns pic16lc72 20* asynchronous 2tcy ns 46 tt1l t1cki low time synchronous, no prescaler 0.5tcy + 20 ns synchronous, with prescaler pic16c72 10* ns pic16lc72 20* asynchronous 2tcy ns 47 tt1p t1cki input period synchronous greater of: 20 m s or t cy + 40 * n ns n = prescale value (1, 2, 4, 8) asynchronous greater of: 20 m s or 4tcy ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting the t1oscen bit) dc 200 khz 48 tcke2tmri delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 21-1 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
pic16c7x ds30390b-page 208 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 21-7: capture/compare/pwm timings (ccp1) table 21-6: capture/compare/pwm requirements (ccp1) param no. sym characteristic min typ? max units conditions 50 tccl ccp1 input low time no prescaler 0.5t cy + 20* ns with prescaler pic16c72 10* ns pic16lc72 20* ns 51 tcch ccp1 input high time no prescaler 0.5t cy + 20* ns with prescaler pic16c72 10* ns pic16lc72 20* ns 52 tccp ccp1 input period 3 t cy + 40 * n ns n = prescale value (1,4 or 16) 53 tccr ccp1 output rise time 10 25 ns 54 tccf ccp1 output fall time 10 25 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 21-1 for load conditions. rc2/ccp1 (capture mode) 50 51 52 53 54 rc2/ccp1 (compare or pwm mode)
1995 microchip technology inc. preliminary ds30390b-page 209 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 21-8: spi mode timing table 21-7: spi mode requirements parameter no. sym characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) t cy + 20 ns 72 tscl sck input low time (slave mode) t cy + 20 ns 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge t cy ns 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 0.5t cy ns 75 tdor sdo data output rise time 10 25 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) 10 25 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 50 ns ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 21-1 for load conditions ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78
pic16c7x ds30390b-page 210 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 21-9: i 2 c bus start/stop bits timing table 21-8: i 2 c bus start/stop bits requirements parameter no. sym characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91 t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92 t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 note: refer to figure 21-1 for load conditions 91 93 scl sda start condition stop condition 90 92
1995 microchip technology inc. preliminary ds30390b-page 211 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 21-10: i 2 c bus data timing table 21-9: i 2 c bus data requirements parameter no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 m s pic16c72 must operate at a minimum of 1.5 mhz 400 khz mode 0.6 m s pic16c72 must operate at a minimum of 10 mhz ssp module 1.5t cy 101 t low clock low time 100 khz mode 4.7 m s pic16c72 must operate at a minimum of 1.5 mhz 400 khz mode 1.3 m s pic16c72 must operate at a minimum of 10 mhz ssp module 1.5t cy 102 t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91 t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107 t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92 t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109 t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110 t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement tsu;dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. note: refer to figure 21-1 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16c7x ds30390b-page 212 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a table 21-10: serial port synchronous transmission requirements table 21-11: serial port synchronous receive requirements parameter no. sym characteristic min typ? max units conditions 120 tckh2dtv sync xmit (master & sla ve) clock high to data out valid pic16c72 50 ns pic16lc72 100 ns 121 tckrf clock out rise time and fall time (master mode) pic16c72 25 ns pic16lc72 50 ns 122 tdtrf data out rise time and fall time pic16c72 25 ns pic16lc72 50 ns ?: data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125 tdtv2ckl sync rcv (master & sla ve) data hold before ck (dt hold time) 15 ns 126 tckl2dtl data hold after ck (dt hold time) 15 ns ?: data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
1995 microchip technology inc. preliminary ds30390b-page 213 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a table 21-12: a/d converter characteristics: pic16c72-04 (commercial, industrial, automotive (3) ) pic16c72-10 (commercial, industrial, automotive (3) ) pic16c72-20 (commercial, industrial, automotive (3) ) parameter no. sym characteristic min typ? max units conditions n r resolution 8-bits v ref = v dd = 5.12v, v ss a in v ref n int integral error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n dif differential error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n fs full scale error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n off offset error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref monotonicity guaranteed v ss a in v ref v ref reference voltage 3.0v v dd + 0.3 v v ain analog input voltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of analog voltage source 10.0 k w i ad a/d conversion cur- rent (v dd ) 180 m a average current consumption when a/d is on. (note 1) i ref v ref input current (note 2) 1 10 ma m a during sampling all other times * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 3: automotive operating range is advanced information for this device.
pic16c7x ds30390b-page 214 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a table 21-13: a/d converter characteristics: pic16lc72-04 (commercial, industrial, automotive (4) ) parameter no. sym characteristic min typ? max units conditions n r resolution 8-bits v ref = v dd = 3.0v (note 1) n int integral error less than 1 lsb ? ref = v dd = 3.0v (note 1) n dif differential error less than 1 lsb ? ref = v dd = 3.0v (note 1) n fs full scale error less than 1 lsb ? ref = v dd = 3.0v (note 1) n off offset error less than 1 lsb ? ref = v dd = 3.0v (note 1) monotonicity guaranteed v ss a in v ref v ref reference voltage 3.0v v dd + 0.3 v v ain analog input voltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of ana- log voltage source 10.0 k w i ad a/d conversion cur- rent (v dd ) ?0 m a average current consumption when a/d is on. (note 2) i ref v ref input current (note 3) 1 10 ma m a during sampling all other times * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: these speci?ations apply if v ref = 3.0v and if v dd 3 3.0v. vin must be between v ss and v ref 2: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 3: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 4: automotive operating range is advanced information for this device.
1995 microchip technology inc. preliminary ds30390b-page 215 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 21-11: a/d conversion timing table 21-14: a/d conversion requirements parameter no. sym characteristic min typ? max units conditions 130 t ad a/d clock period 1.6 2.0 m s m s v ref 3 3.0v v ref full range 130 t ad a/d internal rc oscillator source adcs1:adcs0 = 11 (rc oscillator source) 3.0 6.0 9.0 m s pic16lc72, v dd = 3.0v 2.0 4.0 6.0 m s pic16c72 131 t cnv conversion time (not including s/h time) (note 1) 9.5t ad 132 t smp sampling time note 2 20 m s * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 13.1 for min conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 tcy
pic16c7x ds30390b-page 216 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a notes:
1995 microchip technology inc. preliminary ds30390b-page 217 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 22.0 dc and ac characteristics graphs and tables for pic16c72 not available at this time this document was created with framemake r404
pic16c7x ds30390b-page 218 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a notes:
1995 microchip technology inc. preliminary ds30390b-page 219 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 23.0 electrical characteristics for pic16c73/74 absolute maximum ratings ? ambient temperature under bias................................................................................................................ .-55 to +125?c storage temperature .............................................................................................................................. -65?c to +150?c voltage on any pin with respect to v ss (except v dd and mclr ) ................................................... -0.6v to (v dd + 0.6v) voltage on v dd with respect to v ss ................................................................................................................ 0 to +7.5v voltage on mclr with respect to v ss (note 2) .................................................................................................0 to +14v total power dissipation (note 1)................................................................................................................................1.0w maximum current out of v ss pin ...........................................................................................................................300 ma maximum current into v dd pin ..............................................................................................................................250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..........................................................................................................25 ma maximum output current sourced by any i/o pin ....................................................................................................25 ma maximum current sunk by porta, portb, and porte (combined) (note 3) ...................................................200 ma maximum current sourced by porta, portb, and porte (combined) (note 3) ..............................................200 ma maximum current sunk by portc and portd (combined) (note 3)..................................................................200 ma maximum current sourced by portc and portd (combined) (note 3).............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd - v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow?level to the mclr pin rather than pulling this pin directly to v ss . note 3: portd and porte are not implemented on the pic16c73. ? notice: stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. this document was created with framemake r404
pic16c7x ds30390b-page 220 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a table 23-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) osc pic16c73-04 pic16c74-04 pic16c73-10 pic16c74-10 pic16c73-20 pic16c74-20 pic16lc73-04 pic16lc74-04 jw devices rc v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 2.0 ma typ. at 3.0v i pd : 0.9 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 2.0 ma typ. at 3.0v i pd : 0.9 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v do not use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 10 mhz max. freq: 20 mhz max. freq: 10 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. do not use in lp mode do not use in lp mode v dd : 3.0v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 13.5 m a max. at 3.0v freq: 200 khz max. v dd : 3.0v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 13.5 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recommended that the user select the device type that ensures the speci?ations required.
1995 microchip technology inc. preliminary ds30390b-page 221 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 23.1 dc characteristics: pic16c73-04 (commercial, industrial) pic16c74-04 (commercial, industrial) pic16c73-10 (commercial, industrial) pic16c74-10 (commercial, industrial) pic16c73-20 (commercial, industrial) pic16c74-20 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002 ram data retention voltage (note 1) v dr - 1.5* - v device in sleep mode d003 v dd start voltage to ensure power-on reset v por -v ss - v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05* - - v/ms see section on power-on reset for details d010 d013 supply current (note 2,5) i dd - - 2.7 13.5 5 30 ma ma xt, rc osc con?uration (pic16c74-04) f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con?uration (pic16c74-20) f osc = 20 mhz, v dd = 5.5v d020 d021 d021a power-down current (note 3,5) i pd - - - 10.5 1.5 1.5 42 21 24 m a m a m a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -0 c to +70 c v dd = 4.0v, wdt disabled, -40 c to +85 c * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from charac- terization and is for design guidance only. this is not tested.
pic16c7x ds30390b-page 222 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a 23.2 dc characteristics: pic16lc73-04 (commercial, industrial) pic16lc74-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 3.0 - 6.0 v lp, xt, rc osc con?uration (dc - 4 mhz) d002 ram data retention voltage (note 1) v dr - 1.5* - v device in sleep mode d003 v dd start voltage to ensure power-on reset v por -v ss - v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05* - - v/ms see section on power-on reset for details d010 d010a supply current (note 2,5) i dd - - 2.0 22.5 3.8 48 ma m a xt, rc osc con?uration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con?uration f osc = 32 khz, v dd = 3.0v, wdt disabled d020 d021 d021a power-down current (note 3,5) i pd - - - 7.5 0.9 0.9 30 13.5 18 m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from charac- terization and is for design guidance only. this is not tested.
1995 microchip technology inc. preliminary ds30390b-page 223 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 23.3 dc characteristics: pic16c73-04 (commercial, industrial) pic16c74-04 (commercial, industrial) pic16c73-10 (commercial, industrial) pic16c74-10 (commercial, industrial) pic16c73-20 (commercial, industrial) pic16c74-20 (commercial, industrial) pic16lc73-04 (commercial, industrial) pic16lc74-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 23.1 and section 23.2. param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 with ttl buffer v ss - 0.5v v d031 with schmitt trigger buffer v ss - 0.2v dd v d032 mclr , ra4/t0cki,osc1 (in rc mode) v ss - 0.2v dd v d033 osc1 (in xt, hs and lp) v ss - 0.3v dd v note1 input high voltage i/o ports v ih - d040 with ttl buffer 2.0 - v dd v 4.5v v dd 5.5v d040a 0.8v dd -v dd v for v dd > 5.5v or v dd < 4.5v d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr , ra4/t0cki, rc7:rc4, rd7:rd4, rb0/int 0.8v dd -v dd v d042a re2:re0, osc1 (xt, hs and lp) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 250 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi-imped- ance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc con?uration output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin.
pic16c7x ds30390b-page 224 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a output high voltage d090 i/o ports (note 3) v oh v dd - 0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clkout (rc osc con?) v dd - 0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c capacitive loading specs on output pins d100 osc2 pin c osc2 - - 15 pf in xt, hs and lp modes when exter- nal clock is used to drive osc1. d101 d102 all i/o pins and osc2 (in rc mode) scl, sda in i 2 c mode c io c b - - - - 50 400 pf pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 23.1 and section 23.2. param no. characteristic sym min typ ? max units conditions ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin.
1995 microchip technology inc. preliminary ds30390b-page 225 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 23.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 23-1: load conditions 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 100 pf for portd and porte outputs when used as system bus 50 pf for all pins except osc2, but including portd and porte outputs as ports 15 pf for osc2 output note: portd and porte are not implemented on the pic16c73. load condition 1 load condition 2
pic16c7x ds30390b-page 226 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a 23.5 t iming dia grams and speci cations figure 23-2: external clock timing table 23-2: clock timing requirements parameter no. sym characteristic min typ? max units conditions fos external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (pic16c73-04, pic16c74-04) dc 20 mhz hs osc mode (pic16c73-20, pic16c74-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 4 mhz hs osc mode (pic16c73-04, pic16c74-04) 4 4 5 10 20 200 mhz mhz khz hs osc mode (pic16c73-10, pic16c74-10) hs osc mode (pic16c73-20, pic16c74-20) lp osc mode 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (pic16c73-04, pic16c74-04) 100 ns hs osc mode (pic16c73-10, pic16c74-10) 50 ns hs osc mode (pic16c73-20, pic16c74-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (pic16c73-04, pic16c74-04) 100 50 250 250 ns ns hs osc mode (pic16c73-10, pic16c74-10) hs osc mode (pic16c73-20, pic16c74-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 dc ns t cy = 4/f osc ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
1995 microchip technology inc. preliminary ds30390b-page 227 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 3 tosl, tosh external clock in (osc1) high or low time 50 ns xt oscillator 2.5 m s lp oscillator 10 ns hs oscillator 4 tosr, tosf external clock in (osc1) rise or fall time ? 25 ns xt oscillator ? 50 ns lp oscillator 15 ns hs oscillator table 23-2: clock timing requirements (cont.d) parameter no. sym characteristic min typ? max units conditions ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices.
pic16c7x ds30390b-page 228 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 23-3: clkout and i/o timing table 23-3: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 15 30 ns note 1 11* tosh2ckh osc1 - to clkout - 15 30 ns note 1 12* tckr clkout rise time 5 15 ns note 1 13* tckf clkout fall time 5 15 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - 0.25t cy + 25 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 80 - 100 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) tbd ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) tbd ns 20* tior port output rise time pic16c73/74 10 25 ns pic16lc73/74 60 ns 21* tiof port output fall time pic16c73/74 10 25 ns pic16lc73/74 60 ns 22??* tinp int pin high or low time 20 ns 23??* trbp rb7:rb4 change int high or low time 20 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 23-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
1995 microchip technology inc. preliminary ds30390b-page 229 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 23-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing table 23-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 100 ns v dd = 5v, -40?c to +85?c 31 twdt watchdog timer time-out period (no prescaler) 7* 18 33* ms v dd = 5v, -40?c to +85?c 32 tost oscillation start-up timer period 1024t osc t osc = osc1 period 33 tpwrt power up timer period 28* 72 132* ms v dd = 5v, -40?c to +85?c 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset 100 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 23-1 for load conditions.
pic16c7x ds30390b-page 230 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 23-5: timer0 and timer1 clock timings table 23-5: timer0 and timer1 clock requirements param no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20* ns with prescaler 10* ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20* ns with prescaler 10* ns 42 tt0p t0cki period greater of: 20 m s or t cy + 40 * n ns n = prescale value (1, 2, 4,..., 256) 45 tt1h t1cki high time synchronous, no prescaler 0.5tcy + 20 ns synchronous, with prescaler pic16c73/74 10* ns pic16lc73/74 20* ns asynchronous 2tcy ns 46 tt1l t1cki low time synchronous, no prescaler 0.5tcy + 20 ns synchronous, with prescaler pic16c73/74 10* ns pic16lc73/74 20* ns asynchronous 2tcy ns 47 tt1p t1cki input period synchronous greater of: 20 m s or t cy + 40 * n ns n = prescale value (1, 2, 4, 8) asynchronous greater of: 20 m s or 4tcy ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting the t1oscen bit) dc 200 khz 48 tcke2tmri delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 23-1 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
1995 microchip technology inc. preliminary ds30390b-page 231 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 23-6: capture/compare/pwm timings (ccp1 and ccp2) table 23-6: capture/compare/pwm requirements (ccp1 and ccp2) parameter no. sym characteristic min typ? max units conditions 50 tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20* ns with prescaler pic16c73/74 10* ns pic16lc73/74 20* ns 51 tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20* ns with prescaler pic16c73/74 10* ns pic16lc73/74 20* ns 52 tccp ccp1 and ccp2 input period 3 t cy + 40 * n ns n = prescale value (1,4 or 16) 53 tccr ccp1 and ccp2 output rise time 10 25 ns 54 tccf ccp1 and ccp2 output fall time 10 25 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 23-1 for load conditions. and rc2/ccp1 (capture mode) 50 51 52 53 54 rc1/t1osi/ccp2 and rc2/ccp1 (compare or pwm mode) rc1/t1osi/ccp2
pic16c7x ds30390b-page 232 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 23-7: parallel slave port timing for the pic16c74 only table 23-7: parallel slave port requirements for the pic16c74 only parameter no. sym characteristic min typ? max units conditions 62 tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 63 twrh2dti wr - or cs - to data?n invalid (hold time) pic16c74 20* ns pic16lc74 35* ns 64 trdl2dtv rd and cs to data?ut valid 60 ns 65 trdh2dti rd - or cs to data?ut invalid 10 30 ns ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 23-1 for load conditions re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
1995 microchip technology inc. preliminary ds30390b-page 233 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 23-8: spi mode timing table 23-8: spi mode requirements parameter no. sym characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) t cy + 20 ns 72 tscl sck input low time (slave mode) t cy + 20 ns 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge t cy ns 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 0.5t cy ns 75 tdor sdo data output rise time 10 25 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) 10 25 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 50 ns ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 23-1 for load conditions ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78
pic16c7x ds30390b-page 234 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 23-9: i 2 c bus start/stop bits timing table 23-9: i 2 c bus start/stop bits requirements parameter no. sym characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91 t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92 t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 note: refer to figure 23-1 for load conditions 91 93 scl sda start condition stop condition 90 92
1995 microchip technology inc. preliminary ds30390b-page 235 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 23-10: i 2 c bus data timing table 23-10: i 2 c bus data requirements parameter no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 m s pic16c73/74 must operate at a minimum of 1.5 mhz 400 khz mode 0.6 m s pic16c73/74 must operate at a minimum of 10 mhz ssp module 1.5t cy 101 t low clock low time 100 khz mode 4.7 m s pic16c73/74 must operate at a minimum of 1.5 mhz 400 khz mode 1.3 m s pic16c73/74 must operate at a minimum of 10 mhz ssp module 1.5t cy 102 t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91 t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107 t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92 t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109 t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110 t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement tsu;dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. note: refer to figure 23-1 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16c7x ds30390b-page 236 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 23-11: usart module: synchronous transmission (master/slave) timing table 23-11: serial port synchronous transmission requirements figure 23-12: usart module: synchronous receive (master/slave) timing table 23-12: serial port synchronous receive requirements parameter no. sym characteristic min typ? max units conditions 120 tckh2dtv sync xmit (master & sla ve) clock high to data out valid pic16c73/74 50 ns pic16lc73/74 100 ns 121 tckrf clock out rise time and fall time (master mode) pic16c73/74 25 ns pic16lc73/74 50 ns 122 tdtrf data out rise time and fall time pic16c73/74 25 ns pic16lc73/74 50 ns ?: data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125 tdtv2ckl sync rcv (master & sla ve) data hold before ck (dt hold time) 15 ns 126 tckl2dtl data hold after ck (dt hold time) 15 ns ?: data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 23-1 for load conditions 121 121 122 rc6/tx/ck rc7/rx/dt pin pin 120 note: refer to figure 23-1 for load conditions 125 126 rc6/tx/ck rc7/rx/dt pin pin
1995 microchip technology inc. preliminary ds30390b-page 237 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a table 23-13: a/d converter characteristics: pic16c73-04 (commercial, industrial) pic16c74-04 (commercial, industrial) pic16c73-10 (commercial, industrial) pic16c74-10 (commercial, industrial) pic16c73-20 (commercial, industrial) pic16c74-20 (commercial, industrial) parameter no. sym characteristic min typ? max units conditions n r resolution 8-bits v ref = v dd = 5.12v, v ss a in v ref n int integral error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n dif differential error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n fs full scale error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n off offset error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref monotonicity guaranteed v ss a in v ref v ref reference voltage 3.0v v dd + 0.3 v v ain analog input voltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of analog voltage source 10.0 k w i ad a/d conversion cur- rent (v dd ) 180 m a average current consumption when a/d is on. (note 1) i ref v ref input current (note 2) 1 10 ma m a during sampling all other times * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input.
pic16c7x ds30390b-page 238 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a table 23-14: a/d converter characteristics: pic16lc73-04 (commercial, industrial) pic16lc74-04 (commercial, industrial) parameter no. sym characteristic min typ? max units conditions n r resolution 8-bits v ref = v dd = 3.0v (note 1) n int integral error less than 1 lsb ? ref = v dd = 3.0v (note 1) n dif differential error less than 1 lsb ? ref = v dd = 3.0v (note 1) n fs full scale error less than 1 lsb ? ref = v dd = 3.0v (note 1) n off offset error less than 1 lsb ? ref = v dd = 3.0v (note 1) monotonicity guaranteed v ss a in v ref v ref reference voltage 3.0v v dd + 0.3 v v ain analog input voltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of ana- log voltage source 10.0 k w i ad a/d conversion cur- rent (v dd ) ?0 m a average current consumption when a/d is on. (note 2) i ref v ref input current (note 3) 1 10 ma m a during sampling all other times * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: these speci?ations apply if v ref = 3.0v and if v dd 3 3.0v. v in must be between v ss and v ref 2: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 3: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input.
1995 microchip technology inc. preliminary ds30390b-page 239 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 23-13: a/d conversion timing table 23-15: a/d conversion requirements parameter no. sym characteristic min typ? max units conditions 130 t ad a/d clock period 1.6 2.0 m s m s v ref 3 3.0v v ref full range 130 t ad a/d internal rc oscillator source adcs1:adcs0 = 11 (rc oscillator source) 3.0 6.0 9.0 m s pic16lc73, pic16lc74, v dd = 3.0v 2.0 4.0 6.0 m s pic16c73, pic16c74 131 t cnv conversion time (not including s/h time) (note 1) 9.5t ad 132 t smp sampling time note 2 20 m s * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 13.1 for min conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 tcy
pic16c7x ds30390b-page 240 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a notes:
1995 microchip technology inc. preliminary ds30390b-page 241 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 24.0 dc and ac characteristics graphs and tables for pic16c73/74 not available at this time this document was created with framemake r404
pic16c7x ds30390b-page 242 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a notes:
1995 microchip technology inc. preliminary ds30390b-page 243 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 25.0 electrical characteristics for pic16c73a/74a absolute maximum ratings ? ambient temperature under bias................................................................................................................ .-55 to +125?c storage temperature .............................................................................................................................. -65?c to +150?c voltage on any pin with respect to v ss (except v dd and mclr ) ................................................... -0.6v to (v dd + 0.6v) voltage on v dd with respect to v ss ................................................................................................................ 0 to +7.5v voltage on mclr with respect to v ss (note 2) .................................................................................................0 to +14v total power dissipation (note 1)................................................................................................................................1.0w maximum current out of v ss pin ...........................................................................................................................300 ma maximum current into v dd pin ..............................................................................................................................250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..........................................................................................................25 ma maximum output current sourced by any i/o pin ....................................................................................................25 ma maximum current sunk by porta, portb, and porte (combined) (note 3) ...................................................200 ma maximum current sourced by porta, portb, and porte (combined) (note 3) ..............................................200 ma maximum current sunk by portc and portd (combined) (note 3)..................................................................200 ma maximum current sourced by portc and portd (combined) (note 3).............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd - v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a ?ow?level to the mclr pin rather than pulling this pin directly to v ss . note 3: portd and porte are not implemented on the pic16c73a. ? notice: stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. this document was created with framemake r404
pic16c7x ds30390b-page 244 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a table 25-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) osc pic16c73a-04 pic16c74a-04 pic16c73a-10 pic16c74a-10 pic16c73a-20 pic16c74a-20 pic16lc73a-04 pic16lc74a-04 jw devices rc v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 2.0 ma typ. at 3.0v i pd : 0.9 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 3.0v to 6.0v i dd : 2.0 ma typ. at 3.0v i pd : 0.9 m a typ. at 3v freq: 4 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v do not use in hs mode v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 10 mhz max. freq: 20 mhz max. freq: 10 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. do not use in lp mode do not use in lp mode v dd : 3.0v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v freq: 200 khz max. v dd : 3.0v to 6.0v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recommended that the user select the device type that ensures the speci?ations required.
1995 microchip technology inc. preliminary ds30390b-page 245 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 25.1 dc characteristics: pic16c73a-04 (commercial, industrial, automotive (6) ) pic16c74a-04 (commercial, industrial, automotive (6) ) pic16c73a-10 (commercial, industrial, automotive (6) ) pic16c74a-10 (commercial, industrial, automotive (6) ) pic16c73a-20 (commercial, industrial, automotive (6) ) pic16c74a-20 (commercial, industrial, automotive (6) ) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 - - 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002 ram data retention voltage (note 1) v dr - 1.5* - v device in sleep mode d003 v dd start voltage to ensure power-on reset v por -v ss - v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05* - - v/ms see section on power-on reset for details d010 d013 supply current (note 2,5) i dd - - 2.7 13.5 5 30 ma ma xt, rc osc con?uration (pic16c74a-04) f osc = 4 mhz, v dd = 5.5v (note 4) hs osc con?uration (pic16c74a-20) f osc = 20 mhz, v dd = 5.5v d015 brown-out reset current (note 7) d i bor - 300* 500 m a bor enabled v dd = 5.0v d020 d021 d021a d021b power-down current (note 3,5) i pd - - - - 10.5 1.5 1.5 1.5 42 21 24 tbd m a m a m a m a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -0 c to +70 c v dd = 4.0v, wdt disabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -40 c to +125 c d023 brown-out reset current (note 7) d i bor - 300* 500 m a bor enabled v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from charac- terization and is for design guidance only. this is not tested. 6: automotive operating range is advanced information for this device. 7: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
pic16c7x ds30390b-page 246 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a 25.2 dc characteristics: pic16lc73a-04 (commercial, industrial, automotive (6) ) pic16lc74a-04 (commercial, industrial, automotive (6) ) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 3.0 - 6.0 v lp, xt, rc osc con?uration (dc - 4 mhz) d002 ram data retention voltage (note 1) v dr - 1.5* - v device in sleep mode d003 v dd start voltage to ensure power-on reset v por -v ss - v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05* - - v/ms see section on power-on reset for details d010 d010a supply current (note 2,5) i dd - - 2.0 22.5 3.8 48 ma m a xt, rc osc con?uration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc con?uration f osc = 32 khz, v dd = 3.0v, wdt disabled d015 brown-out reset current (note 7) d i bor - 300* 500 m a bor enabled v dd = 3.0v d020 d021 d021a d021b power-down current (note 3,5) i pd - - - - 7.5 0.9 0.9 0.9 30 5 5 10 m a m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c v dd = 3.0v, wdt disabled, -40 c to +125 c d023 brown-out reset current (note 7) d i bor - 300* 500 m a bor enabled v dd = 3.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the speci?ation. this value is from charac- terization and is for design guidance only. this is not tested. 6: automotive operating range is advanced information for this device. 7: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
1995 microchip technology inc. preliminary ds30390b-page 247 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 25.3 dc characteristics: pic16c73a-04 (commercial, industrial, automotive (4) ) pic16c74a-04 (commercial, industrial, automotive (4) ) pic16c73a-10 (commercial, industrial, automotive (4) ) pic16c74a-10 (commercial, industrial, automotive (4) ) pic16c73a-20 (commercial, industrial, automotive (4) ) pic16c74a-20 (commercial, industrial, automotive (4) ) pic16lc73a-04 (commercial, industrial, automotive (4) ) pic16lc74a-04 (commercial, industrial, automotive (4) ) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 25.1 and section 25.2. param no. characteristic sym min typ ? max units conditions input low voltage i/o ports v il d030 with ttl buffer v ss - 0.5v v d031 with schmitt trigger buffer v ss - 0.2v dd v d032 mclr , ra4/t0cki,osc1 (in rc mode) v ss - 0.2v dd v d033 osc1 (in xt, hs and lp) v ss - 0.3v dd v note1 input high voltage i/o ports v ih - d040 with ttl buffer 2.0 - v dd v 4.5v v dd 5.5v d040a 0.8v dd -v dd v for v dd > 5.5v or v dd < 4.5v d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr , ra4/t0cki, rc7:rc4, rd7:rd4, rb0/int 0.8v dd -v dd v d042a re2:re0, osc1 (xt, hs and lp) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -v dd v d070 portb weak pull-up current i purb 50 250 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il -- 1 m a vss v pin v dd , pin at hi-imped- ance d061 mclr , ra4/t0cki - - 5 m a vss v pin v dd d063 osc1 - - 5 m a vss v pin v dd , xt, hs and lp osc con?uration ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: automotive operating range is advanced information for this device.
pic16c7x ds30390b-page 248 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a output low voltage d080 i/o ports v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc con?) - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a - - 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c output high voltage d090 i/o ports (note 3) v oh v dd - 0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd - 0.7 - - v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc con?) v dd - 0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd - 0.7 - - v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c capacitive loading specs on output pins d100 osc2 pin c osc2 - - 15 pf in xt, hs and lp modes when exter- nal clock is used to drive osc1. d101 d102 all i/o pins and osc2 (in rc mode) scl, sda in i 2 c mode c io c b - - - - 50 400 pf pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40?c t a +125?c for automotive, -40?c t a +85?c for industrial and 0?c t a +70?c for commercial operating voltage v dd range as described in dc spec section 25.1 and section 25.2. param no. characteristic sym min typ ? max units conditions ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c7x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin. 4: automotive operating range is advanced information for this device.
1995 microchip technology inc. preliminary ds30390b-page 249 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 25.4 timing p arameter symbology the timing parameter symbols have been created following one of the following formats: figure 25-1: load conditions 1. tpps2pps 3. t cc : st (i 2 c speci?ations only) 2. tpps 4. ts (i 2 c speci?ations only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c speci?ations only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 100 pf for portd and porte outputs when used as system bus 50 pf for all pins except osc2, but including portd and porte outputs as ports 15 pf for osc2 output note: portd and porte are not implemented on the pic16c73a. load condition 1 load condition 2
pic16c7x ds30390b-page 250 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a 25.5 t iming dia grams and speci cations figure 25-2: external clock timing table 25-2: clock timing requirements parameter no. sym characteristic min typ? max units conditions fos external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (pic16c73a-04, pic16c74a-04) dc 20 mhz hs osc mode (pic16c73a-20, pic16c74a-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 4 mhz hs osc mode (pic16c73a-04, pic16c74a-04) 4 4 5 10 20 200 mhz mhz khz hs osc mode (pic16c73a-10, pic16c74a-10) hs osc mode (pic16c73a-20, pic16c74a-20) lp osc mode 1 tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (pic16c73a-04, pic16c74a-04) 100 ns hs osc mode (pic16c73a-10, pic16c74a-10) 50 ns hs osc mode (pic16c73a-20, pic16c74a-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (pic16c73a-04, pic16c74a-04) 100 50 250 250 ns ns hs osc mode (pic16c73a-10, pic16c74a-10) hs osc mode (pic16c73a-20, pic16c74a-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 dc ns t cy = 4/f osc ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
1995 microchip technology inc. preliminary ds30390b-page 251 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 3 tosl, tosh external clock in (osc1) high or low time 50 ns xt oscillator 2.5 m s lp oscillator 10 ns hs oscillator 4 tosr, tosf external clock in (osc1) rise or fall time ? 25 ns xt oscillator ? 50 ns lp oscillator 15 ns hs oscillator table 25-2: clock timing requirements (cont.d) parameter no. sym characteristic min typ? max units conditions ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices.
pic16c7x ds30390b-page 252 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 25-3: clkout and i/o timing table 25-3: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 15 30 ns note 1 11* tosh2ckh osc1 - to clkout - 15 30 ns note 1 12* tckr clkout rise time 5 15 ns note 1 13* tckf clkout fall time 5 15 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - 0.25t cy + 25 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 80 - 100 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) tbd ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) tbd ns 20* tior port output rise time pic16c73/74 10 25 ns pic16lc73/74 60 ns 21* tiof port output fall time pic16c73/74 10 25 ns pic16lc73/74 60 ns 22??* tinp int pin high or low time 20 ns 23??* trbp rb7:rb4 change int high or low time 20 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 25-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
1995 microchip technology inc. preliminary ds30390b-page 253 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 25-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 25-5: brown-out reset timing table 25-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 1 m sv dd = 5v, -40?c to +125?c 31 twdt watchdog timer time-out period (no prescaler) 7* 18 33* ms v dd = 5v, -40?c to +125?c 32 tost oscillation start-up timer period 1024t osc t osc = osc1 period 33 tpwrt power up timer period 28* 72 132* ms v dd = 5v, -40?c to +125?c 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset 1.1 m s 35 t bor brown-out reset pulse width 100 m s 3.8v v dd 4.2v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 25-1 for load conditions. v dd bv dd 35
pic16c7x ds30390b-page 254 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 25-6: timer0 and timer1 clock timings table 25-5: timer0 and timer1 clock requirements parameter no. sym characteristic min typ? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20* ns with prescaler 10* ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20* ns with prescaler 10* ns 42 tt0p t0cki period t cy + 40 * n ns n = prescale value (1, 2, 4,..., 256) 45 tt1h t1cki high time synchronous, no prescaler 0.5tcy + 20 ns synchronous, with prescaler pic16c73a/74a 10* ns pic16lc73a/74a 20* ns asynchronous 2tcy ns 46 tt1l t1cki low time synchronous, no prescaler 0.5tcy + 20 ns synchronous, with prescaler pic16c73a/74a 10* ns pic16lc73a/74a 20* ns asynchronous 2tcy ns 47 tt1p t1cki input period synchronous t cy + 40* n ns n = prescale value (1, 2, 4, 8) asynchronous 4tcy ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting the t1oscen bit) dc 200 khz 48 tcke2tmri delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 25-1 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
1995 microchip technology inc. preliminary ds30390b-page 255 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 25-7: capture/compare/pwm timings (ccp1 and ccp2) table 25-6: capture/compare/pwm requirements (ccp1 and ccp2) param no. sym characteristic min typ? max units conditions 50 tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20* ns with prescaler pic16c73a/74a 10* ns pic16lc73a/74a 20* ns 51 tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20* ns with prescaler pic16c73a/74a 10* ns pic16lc73a/74a 20* ns 52 tccp ccp1 and ccp2 input period 3 t cy + 40 * n ns n = prescale value (1,4 or 16) 53 tccr ccp1 and ccp2 output rise time 10 25 ns 54 tccf ccp1 and ccp2 output fall time 10 25 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 25-1 for load conditions. and rc2/ccp1 (capture mode) 50 51 52 53 54 rc1/t1osi/ccp2 and rc2/ccp1 (compare or pwm mode) rc1/t1osi/ccp2
pic16c7x ds30390b-page 256 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 25-8: parallel slave port timing for the pic16c74a only table 25-7: parallel slave port requirements for the pic16c74a only parameter no. sym characteristic min typ? max units conditions 62 tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 63 twrh2dti wr - or cs - to data?n invalid (hold time) pic16c74a 20* ns pic16lc74a 35* ns 64 trdl2dtv rd and cs to data?ut valid 60 ns 65 trdh2dti rd - or cs to data?ut invalid 10 30 ns ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 25-1 for load conditions re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
1995 microchip technology inc. preliminary ds30390b-page 257 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 25-9: spi mode timing table 25-8: spi mode requirements parameter no. sym characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) t cy + 20 ns 72 tscl sck input low time (slave mode) t cy + 20 ns 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge t cy ns 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 0.5t cy ns 75 tdor sdo data output rise time 10 25 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) 10 25 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge 50 ns ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 25-1 for load conditions ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78
pic16c7x ds30390b-page 258 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 25-10: i 2 c bus start/stop bits timing table 25-9: i 2 c bus start/stop bits requirements parameter no. sym characteristic min typ max units conditions 90 t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91 t hd : sta start condition 100 khz mode 4000 ns after this period the ?st clock pulse is generated hold time 400 khz mode 600 92 t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 note: refer to figure 25-1 for load conditions 91 93 scl sda start condition stop condition 90 92
1995 microchip technology inc. preliminary ds30390b-page 259 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 25-11: i 2 c bus data timing table 25-10: i 2 c bus data requirements parameter no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 m s pic16c73a/74a must operate at a minimum of 1.5 mhz 400 khz mode 0.6 m s pic16c73a/74a must operate at a minimum of 10 mhz ssp module 1.5t cy 101 t low clock low time 100 khz mode 4.7 m s pic16c73a/74a must operate at a minimum of 1.5 mhz 400 khz mode 1.3 m s pic16c73a/74a must operate at a minimum of 10 mhz ssp module 1.5t cy 102 t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is speci?d to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91 t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the ?st clock pulse is generated 400 khz mode 0.6 m s 106 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107 t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92 t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109 t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110 t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the unde?ed region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement tsu;dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus speci?ation) before the scl line is released. note: refer to figure 25-1 for load conditions 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic16c7x ds30390b-page 260 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a figure 25-12: usart module: synchronous transmission (master/slave) timing table 25-11: serial port synchronous transmission requirements figure 25-13: usart module: synchronous receive (master/slave) timing table 25-12: serial port synchronous receive requirements parameter no. sym characteristic min typ? max units conditions 120 tckh2dtv sync xmit (master & sla ve) clock high to data out valid pic16c73a/74a 50 ns pic16lc73a/74a 100 ns 121 tckrf clock out rise time and fall time (master mode) pic16c73a/74a 25 ns pic16lc73a/74a 50 ns 122 tdtrf data out rise time and fall time pic16c73a/74a 25 ns pic16lc73a/74a 50 ns ?: data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125 tdtv2ckl sync rcv (master & sla ve) data hold before ck (dt hold time) 15 ns 126 tckl2dtl data hold after ck (dt hold time) 15 ns ?: data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 25-1 for load conditions 121 121 122 rc6/tx/ck rc7/rx/dt pin pin 120 note: refer to figure 25-1 for load conditions 125 126 rc6/tx/ck rc7/rx/dt pin pin
1995 microchip technology inc. preliminary ds30390b-page 261 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a table 25-13: a/d converter characteristics: pic16c73a-04 (commercial, industrial, automotive (3) ) pic16c74a-04 (commercial, industrial, automotive (3) ) pic16c73a-10 (commercial, industrial, automotive (3) ) pic16c74a-10 (commercial, industrial, automotive (3) ) pic16c73a-20 (commercial, industrial, automotive (3) ) pic16c74a-20 (commercial, industrial, automotive (3) ) parameter no. sym characteristic min typ? max units conditions n r resolution 8-bits v ref = v dd = 5.12v, v ss a in v ref n int integral error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n dif differential error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n fs full scale error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref n off offset error less than 1 lsb ? ref = v dd = 5.12v, v ss a in v ref monotonicity guaranteed v ss a in v ref v ref reference voltage 3.0v v dd + 0.3 v v ain analog input voltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of analog voltage source 10.0 k w i ad a/d conversion cur- rent (v dd ) 180 m a average current consumption when a/d is on. (note 1) i ref v ref input current (note 2) 1 10 ma m a during sampling all other times * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 3: automotive operating range is advanced information for this device.
pic16c7x ds30390b-page 262 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a table 25-14: a/d converter characteristics: pic16lc73a-04 (commercial, industrial, automotive (4) ) pic16lc74a-04 (commercial, industrial, automotive (4) ) parameter no. sym characteristic min typ? max units conditions n r resolution 8-bits v ref = v dd = 3.0v (note 1) n int integral error less than 1 lsb ? ref = v dd = 3.0v (note 1) n dif differential error less than 1 lsb ? ref = v dd = 3.0v (note 1) n fs full scale error less than 1 lsb ? ref = v dd = 3.0v (note 1) n off offset error less than 1 lsb ? ref = v dd = 3.0v (note 1) monotonicity guaranteed v ss a in v ref v ref reference voltage 3.0v v dd + 0.3 v v ain analog input voltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of ana- log voltage source 10.0 k w i ad a/d conversion cur- rent (v dd ) ?0 m a average current consumption when a/d is on. (note 2) i ref v ref input current (note 3) 1 10 ma m a during sampling all other times * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: these speci?ations apply if v ref = 3.0v and if v dd 3 3.0v. v in must be between v ss and v ref 2: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 3: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 4: automotive operating range is advanced information for this device.
1995 microchip technology inc. preliminary ds30390b-page 263 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a figure 25-14: a/d conversion timing table 25-15: a/d conversion requirements parameter no. sym characteristic min typ? max units conditions 130 t ad a/d clock period 1.6 2.0 m s m s v ref 3 3.0v v ref full range 130 t ad a/d internal rc oscillator source adcs1:adcs0 = 11 (rc oscillator source) 3.0 6.0 9.0 m s pic16lc73a, pic16lc74a, v dd = 3.0v 2.0 4.0 6.0 m s pic16c73a, pic16c74a 131 t cnv conversion time (not including s/h time) (note 1) 9.5t ad 132 t smp sampling time note 2 20 m s * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 13.1 for min conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 tcy
pic16c7x ds30390b-page 264 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a notes:
1995 microchip technology inc. preliminary ds30390b-page 265 pic16c7x applicable devices 70 71 71a 72 73 73a 74 74a 26.0 dc and ac characteristics graphs and tables for pic16c73a/ 74a not available at this time this document was created with framemake r404
pic16c7x ds30390b-page 266 preliminary 1995 microchip technology inc. applicable devices 70 71 71a 72 73 73a 74 74a notes:
1995 microchip technology inc. ds30390b-page 267 pic16c7x 27.0 packaging information 27.1 18-lead cer amic cerdip dual in-line with windo w (300 mil) package group: ceramic cerdip dual in-line (cdp) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 5.080 0.200 a1 0.381 1.7780 0.015 0.070 a2 3.810 4.699 0.150 0.185 a3 3.810 4.445 0.150 0.175 b 0.355 0.585 0.014 0.023 b1 1.270 1.651 typical 0.050 0.065 typical c 0.203 0.381 typical 0.008 0.015 typical d 22.352 23.622 0.880 0.930 d1 20.320 20.320 reference 0.800 0.800 reference e 7.620 8.382 0.300 0.330 e1 5.588 7.874 0.220 0.310 e1 2.540 2.540 reference 0.100 0.100 reference ea 7.366 8.128 typical 0.290 0.320 typical eb 7.620 10.160 0.300 0.400 l 3.175 3.810 0.125 0.150 n 1818 1818 s 0.508 1.397 0.020 0.055 s1 0.381 1.270 0.015 0.050 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a3 a l a c e a e b e1 a2 this document was created with framemake r404
pic16c7x ds30390b-page 268 1995 microchip technology inc. 27.2 28-lead ceramic side braz ed dual in-line with windo w (300 mil) package group: ceramic side brazed dual in-line (cer) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 3.937 5.030 0.155 0.198 a1 1.016 1.524 0.040 0.060 a2 2.921 3.506 0.115 0.138 a3 1.930 2.388 0.076 0.094 b 0.406 0.508 0.016 0.020 b1 1.219 1.321 typical 0.048 0.052 c 0.228 0.305 typical 0.009 0.012 d 35.204 35.916 1.386 1.414 d1 32.893 33.147 reference 1.295 1.305 e 7.620 8.128 0.300 0.320 e1 7.366 7.620 0.290 0.300 e1 2.413 2.667 typical 0.095 0.105 ea 7.366 7.874 reference 0.290 0.310 eb 7.594 8.179 0.299 0.322 l 3.302 4.064 0.130 0.160 n 2828 2828 s 1.143 1.397 0.045 0.055 s1 0.533 0.737 0.021 0.029 e1 e s base plane seating plane b1 b s1 d l a1 a2 a3 a e1 pin #1 indicator area d1 c ea eb a n
1995 microchip technology inc. ds30390b-page 269 pic16c7x 27.3 4 0-lead ceramic cerdip dual in-line wit h windo w (600 mil) package group: ceramic cerdip dual in-line (cdp) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 4.318 5.715 0.170 0.225 a1 0.381 1.778 0.015 0.070 a2 3.810 4.699 0.150 0.185 a3 3.810 4.445 0.150 0.175 b 0.355 0.585 0.014 0.023 b1 1.270 1.651 typical 0.050 0.065 typical c 0.203 0.381 typical 0.008 0.015 typical d 51.435 52.705 2.025 2.075 d1 48.260 48.260 reference 1.900 1.900 reference e 15.240 15.875 0.600 0.625 e1 12.954 15.240 0.510 0.600 e1 2.540 2.540 reference 0.100 0.100 reference ea 14.986 16.002 typical 0.590 0.630 typical eb 15.240 18.034 0.600 0.710 l 3.175 3.810 0.125 0.150 n 4040 4040 s 1.016 2.286 0.040 0.090 s1 0.381 1.778 0.015 0.070 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a3 a a2 l e1 a c e a e b
pic16c7x ds30390b-page 270 1995 microchip technology inc. 27.4 18-lead plastic dual in-line (300 mil) package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 4.064 0.160 a1 0.381 0.015 a2 3.048 3.810 0.120 0.150 b 0.355 0.559 0.014 0.022 b1 1.524 1.524 reference 0.060 0.060 reference c 0.203 0.381 typical 0.008 0.015 typical d 22.479 23.495 0.885 0.925 d1 20.320 20.320 reference 0.800 0.800 reference e 7.620 8.255 0.300 0.325 e1 6.096 7.112 0.240 0.280 e1 2.489 2.591 typical 0.098 0.102 typical ea 7.620 7.620 reference 0.300 0.300 reference eb 7.874 9.906 0.310 0.390 l 3.048 3.556 0.120 0.140 n 1818 1818 s 0.889 0.035 s1 0.127 0.005 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a2 a l e1 a c e a e b
1995 microchip technology inc. ds30390b-page 271 pic16c7x 27.5 28-lead plastic dual in-line ( 300 mil) package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 3.632 4.572 0.143 0.180 a1 0.381 0.015 a2 3.175 3.556 0.125 0.140 b 0.406 0.559 0.016 0.022 b1 1.016 1.651 typical 0.040 0.065 typical b2 0.762 1.016 4 places 0.030 0.040 4 places b3 0.203 0.508 4 places 0.008 0.020 4 places c 0.203 0.331 typical 0.008 0.013 typical d 34.163 35.179 1.385 1.395 d1 33.020 33.020 reference 1.300 1.300 reference e 7.874 8.382 0.310 0.330 e1 7.112 7.493 0.280 0.295 e1 2.540 2.540 typical 0.100 0.100 typical ea 7.874 7.874 reference 0.310 0.310 reference eb 8.128 9.652 0.320 0.380 l 3.175 3.683 0.125 0.145 n 28 - 28 - s 0.584 1.220 0.023 0.048 n pin no. 1 indicator area e1 e s d d1 base plane seating plane a1 a2 a l e1 a c e a e b detail a detail a b2 b1 b b3
pic16c7x ds30390b-page 272 1995 microchip technology inc. 27.6 40-lead pla stic dual in-line (600 mil) package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 5.080 0.200 a1 0.381 0.015 a2 3.175 4.064 0.125 0.160 b 0.355 0.559 0.014 0.022 b1 1.270 1.778 typical 0.050 0.070 typical c 0.203 0.381 typical 0.008 0.015 typical d 51.181 52.197 2.015 2.055 d1 48.260 48.260 reference 1.900 1.900 reference e 15.240 15.875 0.600 0.625 e1 13.462 13.970 0.530 0.550 e1 2.489 2.591 typical 0.098 0.102 typical ea 15.240 15.240 reference 0.600 0.600 reference eb 15.240 17.272 0.600 0.680 l 2.921 3.683 0.115 0.145 n 4040 4040 s 1.270 0.050 s1 0.508 0.020 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a2 a l e1 a c e a e b
1995 microchip technology inc. ds30390b-page 273 pic16c7x 27.7 18-lead plastic surface m ount (soic - wide , 300 mil bod y) package group: plastic soic (so) symbol millimeters inches min max notes min max notes a 0 8 0 8 a 2.362 2.642 0.093 0.104 a1 0.101 0.300 0.004 0.012 b 0.355 0.483 0.014 0.019 c 0.241 0.318 0.009 0.013 d 11.353 11.735 0.447 0.462 e 7.416 7.595 0.292 0.299 e 1.270 1.270 reference 0.050 0.050 reference h 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 l 0.406 1.143 0.016 0.045 n 1818 1818 cp 0.102 0.004 b e n index area chamfer h x 45 a e h 1 2 3 cp h x 45 c l seating plane base plane d a1 a
pic16c7x ds30390b-page 274 1995 microchip technology inc. 27.8 28-lead plastic surface m ount (soic - wide , 300 mil bod y) package group: plastic soic (so) symbol millimeters inches min max notes min max notes a 0 8 0 8 a 2.362 2.642 0.093 0.104 a1 0.101 0.300 0.004 0.012 b 0.355 0.483 0.014 0.019 c 0.241 0.318 0.009 0.013 d 17.703 18.085 0.697 0.712 e 7.416 7.595 0.292 0.299 e 1.270 1.270 typical 0.050 0.050 typical h 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 l 0.406 1.143 0.016 0.045 n 2828 2828 cp 0.102 0.004 b e n index area chamfer h x 45 a e h 1 2 3 cp h x 45 c l seating plane base plane d a1 a
1995 microchip technology inc. ds30390b-page 275 pic16c7x 27.9 20-lead plastic surfa ce mount (ssop - 209 mil bod y 5.30 mm) package group: plastic ssop symbol millimeters inches min max notes min max notes a 0 8 0 8 a 1.730 1.990 0.068 0.078 a1 0.050 0.210 0.002 0.008 b 0.250 0.380 0.010 0.015 c 0.130 0.220 0.005 0.009 d 7.070 7.330 0.278 0.289 e 5.200 5.380 0.205 0.212 e 0.650 0.650 reference 0.026 0.026 reference h 7.650 7.900 0.301 0.311 l 0.550 0.950 0.022 0.037 n 2020 2020 cp - 0.102 - 0.004 index area n h 123 e e b cp d a a1 base plane seating plane l c a
pic16c7x ds30390b-page 276 1995 microchip technology inc. 27.10 28-lead plastic surf ace mount (ssop - 209 mil bod y 5.30 mm) package group: plastic ssop symbol millimeters inches min max notes min max notes a 0 8 0 8 a 1.730 1.990 0.068 0.078 a1 0.050 0.210 0.002 0.008 b 0.250 0.380 0.010 0.015 c 0.130 0.220 0.005 0.009 d 10.070 10.330 0.396 0.407 e 5.200 5.380 0.205 0.212 e 0.650 0.650 reference 0.026 0.026 reference h 7.650 7.900 0.301 0.311 l 0.550 0.950 0.022 0.037 n 2828 2828 cp - 0.102 - 0.004 index area n h 123 e e b cp d a a1 base plane seating plane l c a
1995 microchip technology inc. ds30390b-page 277 pic16c7x 27.11 4 4-lead plas tic leaded chip carrier (square) package group: plastic leaded chip carrier (plcc) symbol millimeters inches min max notes min max notes a 4.191 4.572 0.165 0.180 a1 2.413 2.921 0.095 0.115 d 17.399 17.653 0.685 0.695 d1 16.510 16.663 0.650 0.656 d2 15.494 16.002 0.610 0.630 d3 12.700 12.700 reference 0.500 0.500 reference e 17.399 17.653 0.685 0.695 e1 16.510 16.663 0.650 0.656 e2 15.494 16.002 0.610 0.630 e3 12.700 12.700 reference 0.500 0.500 reference n 4444 4444 cp 0.102 0.004 lt 0.203 0.381 0.008 0.015 s 0.177 .007 b d-e -a- 0.254 d 1 d 3 3 3 -c- -f- -d- 4 9 8 -b- -e- s 0.177 .007 a f-g s s e e 1 -h- -g- 6 2 3 .010 max 1.524 .060 10 2 11 0.508 .020 1.651 .065 r 1.14/0.64 .045/.025 r 1.14/0.64 .045/.025 1.651 .065 0.508 .020 -h- 11 0.254 .010 max 6 min 0.812/0.661 .032/.026 3 -c- 0.64 .025 min 5 0.533/0.331 .021/.013 0.177 .007 m a f-g s , d-e s 1.27 .050 2 sides a s 0.177 .007 b a s d 3 /e 3 d 2 0.101 .004 0.812/0.661 .032/.026 s 0.38 .015 f-g 4 s 0.38 .015 f-g e 2 d -h- a 1 seating plane 2 sides n pics
pic16c7x ds30390b-page 278 1995 microchip technology inc. 27.12 44-lead plastic surfa ce mount (mqfp 10x10 mm bod y 1.6/0.15 mm lead form)) package group: plastic mqfp symbol millimeters inches min max notes min max notes a 0 7 0 7 a 2.000 2.350 0.078 0.093 a1 0.050 0.250 0.002 0.010 a2 1.950 2.100 0.768 0.083 b 0.300 0.450 typical 0.011 0.018 typical c 0.150 0.180 0.006 0.007 d 12.950 13.450 0.510 0.530 d1 9.900 10.100 0.390 0.398 d3 8.000 8.000 reference 0.315 0.315 reference e 12.950 13.450 0.510 0.530 e1 9.900 10.100 0.390 0.398 e3 8.000 8.000 reference 0.315 0.315 reference e 0.800 0.800 0.031 0.032 l 0.730 1.030 0.028 0.041 n 4444 4444 cp 0.102 0.004 index area 9 b typ 4x base plane a 2 e b a a 1 seating plane 6 d d 1 d 3 4 5 7 e 3 e 1 e 10 0.20 m a-b 0.05 mm/mm d hs s d 0.20 m a-b cs s d 7 5 4 0.20 m a-b cs s d 0.20 m a-b hs s d 0.05 mm/mm a-b c l 1.60 ref. 0.13/0.30 r 0.13 r min. 0.20 min. parting line a
1995 microchip technology inc. ds30390b-page 279 pic16c7x 27.13 44-lead plastic surface mount (tqfp 10x10 mm bod y 1.0/0.10 mm lead form) note 1: dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.25m/m (0.010? per side. d1 and e1 dimensions including mold mismatch. 2: dimension ??does not include dambar protrusion, allowable dambar protrusion shall be 0.08m/m (0.003?max. 3: this outline conforms to jedec ms-026. package group: plastic tqfp symbol millimeters inches min max notes min max notes a 1.00 1.20 0.039 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 d 11.75 12.25 0.463 0.482 d1 9.90 10.10 0.390 0.398 e 11.75 12.25 0.463 0.482 e1 9.90 10.10 0.390 0.398 l 0.45 0.75 0.018 0.030 e 0.80 bsc 0.031 bsc b 0.30 0.45 0.012 0.018 b1 0.30 0.40 0.012 0.016 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 n 4444 4444 q 0 7 0 7 d e d1 e1 pin#1 2 e 1.0?(0.039? ref. option 1 (top side) pin#1 2 option 2 (top side) 3.0?(0.118? ref. detail a detail b l 1.00 ref. a2 a1 a b b1 c c1 base metal detail a lead finish detail b 11 /13 (4x) 0 min 11 /13 (4x) q r1 0.08 min r 0.08/0.20 gage plane 0.250 l l1 s 0.20 min 1.00 ref detail b
pic16c7x ds30390b-page 280 1995 microchip technology inc. 27.14 p ac ka g e marking inf ormation legend: mm...m xx...x aa bb c d 1 e microchip part number information customer speci? information* year code (last 2 digits of calender year) week code (week of january 1 is week '01? facility code of the plant at which wafer is manufactured. c = chandler, arizona, u.s.a. mask revision number for microcontroller assembly code of the plant or country of origin in which part was assembled. in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. note : standard otp marking consists of microchip part number, year code, week code, facility code, mask revision number, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. * mmmmmmmmmmmmm xxxxxxxxxxxxxxxx aabbcde 18-lead pdip 18-lead soic xxxxxxxxxxxx aabbcde xxxxxxxxxxxx mmmmmmmmmm mmmmmm xxxxxxxx aabbcde 18-lead cerdip windowed pic16c71-04/p 9452cba example example -20/50 9447cba pic16c71 pic16c71 /jw 945/cbt example s = tempe, arizona, u.s.a. aabbcae xxxxxxxxxxxx xxxxxxxxxxxx 28-lead ssop 9517sbp 20i/ss025 pic16c72 example aabbcae xxxxxxxx xxxxxxxx 20-lead ssop 9517sbp 20i/ss025 PIC16C70 example
1995 microchip technology inc. ds30390b-page 281 pic16c7x package marking information (contd) legend: mm...m xx...x aa bb c d 1 e microchip part number information customer speci? information* year code (last 2 digits of calender year) week code (week of january 1 is week '01? facility code of the plant at which wafer is manufactured. c = chandler, arizona, u.s.a. mask revision number for microcontroller assembly code of the plant or country of origin in which part was assembled. in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. note : standard otp marking consists of microchip part number, year code, week code, facility code, mask revision number, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. * 28-lead soic xxxxxxxxxxxxxxxxxxxx aabbcde mmmmmmmmmmmmmmmm example 945/caa pic16c73-10/so s = tempe, arizona, u.s.a. xxxxxxxxxxxxxxx aabbcde 28-lead pdip (skinny dip) mmmmmmmmmmmm aabbcde example pic16c73-10/sp example 28-lead side brazed skinny windowed xxxxxxxxxxx xxxxxxxxxxx aabbcde pic16c73/jw 9517cat xxxxxxxxxxxxxxxxxx aabbcde 40-lead pdip mmmmmmmmmmmmmm 9512caa example pic16c74-04/p
pic16c7x ds30390b-page 282 1995 microchip technology inc. package marking information (contd) legend: mm...m xx...x aa bb c d 1 e microchip part number information customer speci? information* year code (last 2 digits of calender year) week code (week of january 1 is week '01? facility code of the plant at which wafer is manufactured. c = chandler, arizona, u.s.a. mask revision number for microcontroller assembly code of the plant or country of origin in which part was assembled. in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. note : standard otp marking consists of microchip part number, year code, week code, facility code, mask revision number, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. * 44-lead plcc mmmmmmmm aabbcde xxxxxxxxxx xxxxxxxxxx 44-lead mqfp xxxxxxxxxx aabbcde mmmmmmmm xxxxxxxxxx example pic16c74 aabbcde -10/l example -10/pq aabbcde pic16c74 s = tempe, arizona, u.s.a. 44-lead tqfp xxxxxxxxxx aabbcde mmmmmmmm xxxxxxxxxx example -10/tq aabbcde pic16c74a mmmmmmmmm xxxxxxxxxxx aabbcde 40-lead cerdip windowed xxxxxxxxxxx pic16c74/jw aabbcde example
1995 microchip technology inc. ds30390b-page 283 pic16c7x appendix a: the following are the list of modi?ations over the pic16c5x microcontroller family: 1. instruction word length is increased to 14-bits. this allows larger page sizes both in program memory (4k now as opposed to 512 before) and register ?e (192 bytes now versus 32 bytes before). 2. a pc high latch register (pclath) is added to handle program memory paging. bits pa2, pa1, pa0 are removed from status register. 3. data memory paging is rede?ed slightly. sta- tus register is modi?d. 4. four new instructions have been added: return, retfie, addlw , and sublw . two instructions tris and option are being phased out although they are kept for compati- bility with pic16c5x. 5. option and tris registers are made address- able. 6. interrupt capability is added. interrupt vector is at 0004h. 7. stack size is increased to 8 deep. 8. reset vector is changed to 0000h. 9. reset of all registers is revisited. five different reset (and wake-up) types are recognized. reg- isters are reset differently. 10. wake up from sleep through interrupt is added. 11. two separate timers, oscillator start-up timer (ost) and power-up timer (pwrt) are included for more reliable power-up. these tim- ers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. portb has weak pull-ups and interrupt on change feature. 13. t0cki pin is also a port pin (ra4) now. 14. fsr is made a full eight bit register. 15. ?n-circuit serial programming?is made possible. the user can program pic16cxx devices using only ?e pins: v dd , v ss , mclr /v pp , rb6 (clock) and rb7 (data in/out). 16. pcon status register is added with a power-on reset status bit (por ). 17. code protection scheme is enhanced such that portions of the program memory can be pro- tected, while the remainder is unprotected. appendix b: compatibility to convert code written for pic16c5x to pic16cxx, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call , goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. rede?e data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to 0000h. this document was created with framemake r404
pic16c7x ds30390b-page 284 1995 microchip technology inc. appendix c: whats new the format of this data sheet has been changed to be consistent with other product families. this ensures that important topics are covered across all pic16/17 microcontroller families. here is an overview list of new features: added the following devices: PIC16C70 pic16c71a pic16c72 pic16c73a pic16c74a the above devices have an on-chip brown-out detect circuit added. a brown-out detect enable bit (boden) has been added to the con?uration word register. a brown-out reset detect bit (bor ) has been added to the pcon register (for the devices with brown-out detect circuitry). a mclr ?ter circuit has been added to minimize the in?ence of pin state changes to the mclr line. appendix d: whats changed all product and device family tables have been updated for the latest devices and speci?ations. tx8/9 (txsta<6>) has been changed to tx9 - 9-bit transmit enable bit. rc8/9 (rcsta<6>) has been changed to rx9 - 9-bit receive enable bit. rcd8 (rcsta<0>) has been changed to rx9d. txd8 (txsta<0>) has been changed to tx9d.
1995 microchip technology inc. ds30390b-page 285 pic16c7x appendix e: pic16/17 microcontrollers table e-1: pic16c5x family of devices pic16c54 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c54a 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54 (2) 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54a 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54b (1) 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c55 20 512 24 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c56 20 1k 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr56 (1) 20 1k 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c57 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16cr57a (2) 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16cr57b 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c58a 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr58a 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr58b (1) 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. note 1: please contact your local sales of?e for availability of these devices. 2: not recommended for new designs. maximum frequency of operation (mhz) eprom rom ram data memory (bytes) timer module(s) i/o pins voltage range (volts) number of instructions packages program memory clock memory peripherals features (words) this document was created with framemake r404
pic16c7x ds30390b-page 286 1995 microchip technology inc. table e-2: pic16c62x family of devices pic16c620 20 512 80 tmr0 2 yes 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c621 20 1k 80 tmr0 2 yes 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c622 20 2k 128 tmr0 2 yes 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) comparator(s) internal reference voltage interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features in-circuit serial programming
1995 microchip technology inc. ds30390b-page 287 pic16c7x table e-3: pic16c6x family of devices pic16c61 20 1k 36 tmr0 3 13 3.0-6.0 yes 18-pin dip, soic pic16c62 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 3.0-6.0 yes 28-pin sdip, soic, ssop pic16c62a (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 3.0-6.0 yes yes 28-pin sdip, soic, ssop pic16cr62 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 3.0-6.0 yes yes 28-pin sdip, soic, ssop pic16c63 (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 10 22 3.0-6.0 yes yes 28-pin sdip, soic pic16c64 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c64a (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 3.0-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp pic16cr64 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 3.0-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp pic16c65 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c65a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 3.0-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect, and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features rom in-circuit serial programming
pic16c7x ds30390b-page 288 1995 microchip technology inc. table e-4: pic16c7x family of devices PIC16C70 (1) 20 512 36 tmr0 4 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c71 20 1k 36 tmr0 4 4 13 3.0-6.0 yes 18-pin dip, soic pic16c71a (1) 20 1k 68 tmr0 4 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c72 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 5 8 22 3.0-6.0 yes yes 28-pin sdip, soic, ssop pic16c73 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 3.0-6.0 yes 28-pin sdip, soic pic16c73a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 3.0-6.0 yes yes 28-pin sdip, soic pic16c74 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c74a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 3.0-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port a/d converter (8-bit) channels interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features in-circuit serial programming
1995 microchip technology inc. ds30390b-page 289 pic16c7x table e-5: pic16c8x family of devices pic16c83 (1) 10 512 36 64 tmr0 4 13 yes 2.0-6.0 18-pin dip, soic pic16cr83 (1) 10 512 36 64 tmr0 4 13 yes 2.0-6.0 18-pin dip, soic pic16c84 10 1k 36 64 tmr0 4 13 yes 2.0-6.0 18-pin dip, soic pic16c84a (1) 10 1k 68 64 tmr0 4 13 yes 2.0-6.0 18-pin dip, soic pic16cr84 (1) 10 1k 68 64 tmr0 4 13 yes 2.0-6.0 18-pin dip, soic all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect, and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eeprom data eeprom (bytes) data memory (bytes) timer module(s) interrupt sources i/o pins voltage range (volts) packages program memory clock memory peripherals features rom in-circuit serial programming
pic16c7x ds30390b-page 290 1995 microchip technology inc. table e-6: pic17cxx family of devices pic17c42 25 2k 232 tmr0,tmr1, tmr2,tmr3 2 2 yes yes 11 33 4.5-5.5 yes 55 40-pin dip; 44-pin plcc, mqfp pic17c43 25 4k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes 11 33 2.5-6.0 yes yes 58 40-pin dip; 44-pin plcc, tqfp pic17c44 25 8k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes 11 33 2.5-6.0 yes yes 58 40-pin dip; 44-pin plcc, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. maximum frequency of operation (mhz) eprom ram data memory (bytes) timer module(s) captures serial port(s) (usart) external interrupts interrupt sources i/o pins voltage range (volts) number of instructions packages program memory clock memory peripherals features pwms in-circuit serial programming hardware multiply
1995 microchip technology inc. ds30390b-page 291 pic16c7x e.1 pin compatibility devices that have the same package type and v dd , v ss and mclr pin locations are said to be pin compatible. this allows these different devices to operate in the same socket. compatible devices may only requires minor software modi?ation to allow proper operation in the application socket (ex., pic16c56 and pic16c61 devices). not all devices in the same package size are pin compatible; for example, the pic16c62 is compatible with the pic16c63, but not the pic16c55. pin compatibility does not mean that the devices offer the same features. as an example, the pic16c54 is pin compatible with the pic16c71, but does not have an a/d converter, weak pull-ups on portb, or interrupts. table e-7: pin compatible devices pin compatible devices package pic16c54, pic16c54a, pic16cr54, pic16cr54a, pic16cr54b, pic16c56, pic16cr56, pic16c58a, pic16cr58a, pic16cr58b, pic16c61, pic16c620, pic16c621, pic16c622, PIC16C70, pic16c71, pic16c71a pic16c83, pic16cr83, pic16c84, pic16c84a, pic16cr84 18 pin (20 pin) pic16c55, pic16cr55, pic16c57, pic16cr57a, pic16cr57b 28 pin pic16c62, pic16cr62, pic16c62a, pic16c63, pic16c72, pic16c73, pic16c73a 28 pin pic16c64, pic16cr64, pic16c64a, pic16c65, pic16c65a, pic16c74, pic16c74a 40 pin pic17c42, pic17c43, pic17c44 40 pin
pic16c7x ds30390b-page 292 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30390b-page 293 pic16c7x index a a/d accuracy/error ......................................................... 118 adcon0 register .................................................... 109 adcon1 register .................................................... 111 adif bit .................................................................... 112 analog input model block diagram .......................... 114 analog-to-digital converter ...................................... 109 block diagram .......................................................... 113 configuring analog port pins ................................... 115 configuring the interrupt .......................................... 112 configuring the module ............................................ 112 connection considerations ...................................... 119 conversion clock ..................................................... 115 conversion time ...................................................... 117 conversions ............................................................. 116 converter characteristics ........ 170, 185, 213, 237, 261 delays ...................................................................... 114 effects of a reset ..................................................... 118 equations ................................................................. 114 faster conversion - lower resolution tradeoff ...... 117 flowchart of a/d operation ...................................... 119 go/done bit ........................................................... 112 internal sampling switch (rss) impedence ............. 114 operation during sleep ........................................... 118 sampling requirements ........................................... 114 sampling time ......................................................... 114 source impedence ................................................... 114 time delays ............................................................. 114 transfer function ..................................................... 119 using the ccp trigger ............................................. 118 absolute maximum ratings ............. 159, 175, 197, 219, 243 ack ........................................................................ 84, 88, 89 adcs0 bit ........................................................................ 109 adcs1 bit ........................................................................ 109 addlw instruction .......................................................... 143 addwf instruction .......................................................... 143 adie bit ........................................................................ 32, 34 adif bit ...................................................................... 36, 109 adon bit .......................................................................... 109 adres register .......................................... 26, 28, 109, 112 alu ...................................................................................... 9 andlw instruction .......................................................... 143 andwf instruction .......................................................... 143 application notes an546 ...................................................................... 109 an552 ........................................................................ 45 an556 ........................................................................ 41 an578 ........................................................................ 77 an594 ........................................................................ 71 architecture harvard ........................................................................ 9 overview ...................................................................... 9 von neumann ............................................................... 9 assembler ........................................................................ 156 b baud rate error ................................................................. 95 baud rate formula ............................................................ 95 baud rates .................................................................. 96, 97 bcf instruction ................................................................ 144 bf bit ...................................................................... 77, 88, 89 block diagrams a/d ............................................................................113 analog input model ...................................................114 capture .......................................................................73 compare .....................................................................73 interrupt logic ...........................................................134 on-chip reset circuit ...............................................126 PIC16C70 ...................................................................10 pic16c71 ...................................................................10 pic16c71a .................................................................10 pic16c72 ...................................................................11 pic16c73 ...................................................................12 pic16c73a .................................................................12 pic16c74 ...................................................................13 pic16c74a .................................................................13 portc .......................................................................47 portd (in i/o port mode) .........................................49 portd and porte as a parallel slave port ............54 porte (in i/o port mode) .........................................52 pwm ...........................................................................74 ra3:ra0 and ra5 port pins ......................................43 ra4/t0cki pin ...........................................................44 rb3:rb0 port pins .....................................................45 rb7:rb4 port pins .....................................................45 spi master/slave connection .....................................80 ssp (i 2 c mode) ..........................................................87 ssp (spi mode) .........................................................79 timer0 ........................................................................59 timer0/wdt prescaler ...............................................62 timer1 ........................................................................66 timer2 ........................................................................69 usart receive .......................................................101 usart transmit ........................................................99 watchdog timer .......................................................137 boden bit ........................................................................122 bor bit .......................................................................40, 128 brgh bit ......................................................................93, 95 bsf instruction .................................................................144 btfsc instruction ............................................................144 btfss instruction ............................................................145 c c bit ....................................................................................30 c compiler (mp-c) ...................................................153, 157 call instruction ...............................................................145 capture/compare/pwm capture block diagram ....................................................73 ccp1con register ...........................................72 ccp1if ...............................................................72 ccpr1 ...............................................................72 ccpr1h:ccpr1l .............................................72 mode ..................................................................72 prescaler ............................................................73 ccp timer resources ................................................71 compare block diagram ....................................................73 mode ..................................................................73 software interrupt mode .....................................73 special event trigger .........................................73 special trigger output of ccp1 .........................73 special trigger output of ccp2 .........................73 interaction of two ccp modules ................................71 this document was created with framemake r404
pic16c7x ds30390b-page 294 1995 microchip technology inc. pwm block diagram .................................................... 74 ccp1con ......................................................... 74 duty cycle .......................................................... 74 example frequencies and resolutions ............. 74 mode .................................................................. 74 period ................................................................. 74 section ....................................................................... 71 special event trigger and a/d conversions .............. 73 carry bit ................................................................................ 9 ccp1ie bit ......................................................................... 34 ccp1if bit .................................................................... 36, 37 ccp2ie bit ......................................................................... 38 ccp2if bit .......................................................................... 39 ccpr1h register ........................................................ 28, 71 ccpr1l register ............................................................... 71 ccpr2h register ........................................................ 28, 71 ccpr2l register ......................................................... 28, 71 ccpxm0 bit ........................................................................ 72 ccpxm1 bit ........................................................................ 72 ccpxm2 bit ........................................................................ 72 ccpxm3 bit ........................................................................ 72 ccpxx bit ........................................................................... 72 ccpxy bit ........................................................................... 72 chs0 bit ........................................................................... 109 chs1 bit ........................................................................... 109 ckp bit ............................................................................... 78 clocking scheme ............................................................... 20 clrf instruction .............................................................. 145 clrw instruction ............................................................. 145 clrwdt instruction ........................................................ 146 code examples call of a subroutine in page 1 from page 0 ............... 42 changing between capture prescalers ..................... 73 changing prescaler (timer0 to wdt) ........................ 63 changing prescaler (wdt to timer0) ........................ 63 doing an a/d conversion ........................................ 116 i/o programming ........................................................ 53 indirect addressing .................................................... 42 initializing porta ...................................................... 43 initializing portb ...................................................... 45 initializing portc ...................................................... 47 loading the sspbuf register .................................. 79 saving w register and status in ram .................. 136 code protection ....................................................... 121, 139 comf instruction ............................................................. 146 computed goto ............................................................... 41 configuration bits ............................................................. 121 configuration word .......................................................... 122 cp0 bit ............................................................................. 122 cp1 bit ............................................................................. 122 cren bit ............................................................................ 94 cs pin ................................................................................ 54 csrc bit ............................................................................ 93 d d/a bit ................................................................................ 77 dc bit ................................................................................. 30 dc characteristics PIC16C70 ................................................................ 161 pic16c71 ................................................................ 176 pic16c71a .............................................................. 161 pic16c72 ................................................................ 199 pic16c73 ................................................................ 221 pic16c73a .............................................................. 245 pic16c74 ................................................................ 221 pic16c74a .............................................................. 245 decf instruction ............................................................. 146 decfsz instruction ......................................................... 146 development support .................................................. 5, 153 development systems ..................................................... 157 development tools .......................................................... 153 diagrams - see block diagrams digit carry bit ....................................................................... 9 direct addressing .............................................................. 42 dynamic data exchange (dde) ...................................... 153 e electrical characteristics PIC16C70 ................................................................ 159 pic16c71 ................................................................ 175 pic16c71a .............................................................. 159 pic16c72 ................................................................ 197 pic16c73 ................................................................ 219 pic16c73a .............................................................. 243 pic16c74 ................................................................ 219 pic16c74a .............................................................. 243 external brown-out protection circuit .............................. 132 external power-on reset circuit ...................................... 132 f family of devices pic16c5x ................................................................ 285 pic16c62x .............................................................. 286 pic16c6x ................................................................ 287 pic16c7x ............................................................ 6, 288 pic16c8x ................................................................ 289 pic17cxx ............................................................... 290 ferr bit ............................................................................ 94 fosc0 bit ........................................................................ 122 fosc1 bit ........................................................................ 122 fsr register ............................................. 26, 27, 28, 29, 42 fuzzy logic dev. system ( fuzzy tech -mp) ......... 153, 157 g general description ............................................................. 5 gie bit ........................................................................ 32, 133 go/done bit ................................................................... 109 goto instruction ............................................................. 147 graphs and charts, pic16c71 ........................................ 189 i i/o ports porta ...................................................................... 43 portb ...................................................................... 45 portc ...................................................................... 47 portd ................................................................ 49, 54 porte ...................................................................... 51 section ....................................................................... 43 i/o programming considerations ...................................... 53 i 2 c, see synchronous serial port ibf bit ................................................................................ 54 idle_mode ...................................................................... 92 incf instruction ............................................................... 147 incfsz instruction .......................................................... 147 in-circuit serial programming .................................. 121, 139 indf register ................................ 25??, 25, 27, 28, 29, 42 indirect addressing ............................................................ 42 initialization condition for all register .............................. 129 instruction cycle ................................................................ 20 instruction flow/pipelining ................................................. 20 instruction format ............................................................ 141
1995 microchip technology inc. ds30390b-page 295 pic16c7x instruction set addlw .................................................................... 143 addwf .................................................................... 143 andlw .................................................................... 143 andwf .................................................................... 143 bcf .......................................................................... 144 bsf .......................................................................... 144 btfsc ..................................................................... 144 btfss ..................................................................... 145 call ........................................................................ 145 clrf ........................................................................ 145 clrw ...................................................................... 145 clrwdt .................................................................. 146 comf ...................................................................... 146 decf ....................................................................... 146 decfsz ................................................................... 146 goto ...................................................................... 147 incf ......................................................................... 147 incfsz .................................................................... 147 iorlw ..................................................................... 147 iorwf ..................................................................... 148 movf ....................................................................... 148 movlw ................................................................... 148 movwf ................................................................... 148 nop ......................................................................... 149 option ................................................................... 149 retfie .................................................................... 149 retlw .................................................................... 149 return .................................................................. 150 rlf .......................................................................... 150 rrf .......................................................................... 150 sleep ..................................................................... 150 sublw .................................................................... 151 subwf .................................................................... 151 swapf .................................................................... 152 tris ......................................................................... 152 xorlw .................................................................... 152 xorwf .................................................................... 152 section ..................................................................... 141 summary table ........................................................ 142 int interrupt ..................................................................... 136 intcon register ............................................................... 32 inte bit .............................................................................. 32 intedg bit ................................................................. 31, 136 inter-integrated circuit (i 2 c) ............................................... 77 internal sampling switch (rss) impedence ..................... 114 interrupts .......................................................................... 121 a/d ........................................................................... 133 ccp1 ....................................................................... 133 ccp2 ....................................................................... 133 portb change .......................................................... 136 psp .......................................................................... 133 rb7:rb4 port change ............................................... 45 section ..................................................................... 133 ssp .......................................................................... 133 tmr0 ....................................................................... 136 tmr1 overflow ........................................................ 133 tmr2 matches pr2 ................................................. 133 usart rx ............................................................... 133 usart tx ............................................................... 133 intf bit .............................................................................. 32 iorlw instruction ............................................................ 147 iorwf instruction ........................................................... 148 irp bit ................................................................................ 30 l loading of pc .................................................................... 41 m mclr .......................................................................126, 129 memory data memory ..............................................................22 program memory ........................................................21 program memory maps PIC16C70 ...........................................................21 pic16c71 ...........................................................21 pic16c71a ........................................................21 pic16c72 ...........................................................22 pic16c73 ...........................................................22 pic16c73a ........................................................22 pic16c74 ...........................................................22 pic16c74a ........................................................22 register file maps PIC16C70 ...........................................................23 pic16c71 ...........................................................23 pic16c71a ........................................................23 pic16c72 ...........................................................24 pic16c73 ...........................................................24 pic16c73a ........................................................24 pic16c74 ...........................................................24 pic16c74a ........................................................24 movf instruction ..............................................................148 movlw instruction ..........................................................148 movwf instruction ..........................................................148 mpasm assembler ..................................................153, 156 mp-c c compiler .............................................................157 mpsim software simulator ......................................153, 157 n nop instruction ................................................................149 o obf bit ...............................................................................54 oerr bit ............................................................................94 opcode .............................................................................141 option instruction ..........................................................149 option register ...............................................................31 orthogonal ............................................................................9 osc selection ...................................................................121 oscillator hs .....................................................................123, 128 lp .....................................................................123, 128 rc ............................................................................123 xt .....................................................................123, 128 oscillator configurations ..................................................123 output of tmr2 ..................................................................69 p p bit ....................................................................................77 packaging 18-lead cerdip w/window ....................................267 18-lead pdip ...........................................................270 18-lead soic ...........................................................273 20-lead ssop .........................................................275 28-lead ceramic w/window .....................................268 28-lead pdip ...........................................................271 28-lead soic ...........................................................274 28-lead ssop .........................................................276 40-lead cerdip w/window ....................................269 40-lead pdip ...........................................................272 44-lead mqfp .........................................................278 44-lead plcc ..........................................................277 44-lead tqfp ..........................................................279 paging, program memory ...................................................41
pic16c7x ds30390b-page 296 1995 microchip technology inc. parallel slave port ........................................................ 49, 54 pcfg0 bit ........................................................................ 111 pcfg1 bit ........................................................................ 111 pcfg2 bit ........................................................................ 111 pcl register ........................................ 25, 26, 27, 28, 29, 41 pclath ........................................................................... 129 pclath register ................................. 25, 26, 27, 28, 29, 41 pcon register .......................................................... 40, 128 pd bit ................................................................. 30, 126, 128 picdem-1 low-cost pic16/17 demo board ........... 153, 155 picdem-2 low-cost pic16cxx demo board ........ 153, 155 picmaster probes ........................................................ 154 picmaster system configuration ................................. 153 picmaster ? rt in-circuit emulator ............................. 153 picstart ? low-cost development system ......... 153, 155 pie1 register ..................................................................... 34 pie2 register ..................................................................... 38 pin compatible devices ................................................... 291 pin functions mclr /v pp .......................................... 14, 15, 16, 17, 18 osc1/clkin ...................................... 14, 15, 16, 17, 18 osc2/clkout .................................. 14, 15, 16, 17, 18 ra0/an0 ............................................ 14, 15, 16, 17, 18 ra1/an1 ............................................ 14, 15, 16, 17, 18 ra2/an2 ............................................ 14, 15, 16, 17, 18 ra3/an3/v ref ................................... 14, 15, 16, 17, 18 ra4/t0cki ......................................... 14, 15, 16, 17, 18 ra5/an4/ss .................................................. 16, 17, 18 rb0/int ............................................. 14, 15, 16, 17, 18 rb1 .................................................... 14, 15, 16, 17, 18 rb2 .................................................... 14, 15, 16, 17, 18 rb3 .................................................... 14, 15, 16, 17, 18 rb4 .................................................... 14, 15, 16, 17, 18 rb5 .................................................... 14, 15, 16, 17, 18 rb6 .................................................... 14, 15, 16, 17, 18 rb7 .................................................... 14, 15, 16, 17, 18 rc0/t1oso/t1cki ....................................... 16, 17, 19 rc1/t1osi ................................................................ 16 rc1/t1osi/ccp2 ................................................ 17, 19 rc2/ccp1 ..................................................... 16, 17, 19 rc3/sck/scl ............................................... 16, 17, 19 rc4/sdi/sda ................................................ 16, 17, 19 rc5/sdo ....................................................... 16, 17, 19 rc6 ............................................................................ 16 rc6/tx/ck ............................................ 17, 19, 93?07 rc7 ............................................................................ 16 rc7/rx/dt ............................................ 17, 19, 93?07 rd0/psp0 .................................................................. 19 rd1/psp1 .................................................................. 19 rd2/psp2 .................................................................. 19 rd3/psp3 .................................................................. 19 rd4/psp4 .................................................................. 19 rd5/psp5 .................................................................. 19 rd6/psp6 .................................................................. 19 rd7/psp7 .................................................................. 19 re0/rd /an5 .............................................................. 19 re1/wr /an6 ............................................................. 19 re2/cs /an7 .............................................................. 19 v dd .................................................... 14, 15, 16, 17, 19 v ss ..................................................... 14, 15, 16, 17, 19 pinout descriptions PIC16C70 ............................................................ 14, 15 pic16c71 ............................................................ 14, 15 pic16c71a .......................................................... 14, 15 pic16c72 .................................................................. 16 pic16c73 .................................................................. 17 pic16c73a ................................................................ 17 pic16c74 .................................................................. 18 pic16c74a ................................................................ 18 pir1 register .................................................................... 36 pir2 register .................................................................... 39 pop ................................................................................... 41 por ......................................................................... 127, 128 oscillator start-up timer (ost) ....................... 121, 127 power control register (pcon) .............................. 128 power-on reset (por) ............................ 121, 127, 129 power-up timer (pwrt) ................................. 121, 127 power-up-timer (pwrt) ........................................ 127 time-out sequence ................................................. 128 time-out sequence on power-up ............................ 131 to .................................................................... 126, 128 por bit ...................................................................... 40, 128 port rb interrupt .............................................................. 136 porta ............................................................................ 129 porta register .............................................. 25, 26, 28, 43 portb ............................................................................ 129 portb register .............................................. 25, 26, 28, 45 portc ............................................................................ 129 portc register .................................................... 26, 28, 47 portd ............................................................................ 129 portd register .......................................................... 28, 49 porte ............................................................................ 129 porte register .......................................................... 28, 51 power-down mode (sleep) ............................................ 138 pr2 register ............................................................... 29, 69 prescaler, switching between timer0 and wdt ............... 63 pro mate ? universal programmer ...................... 153, 155 probes ............................................................................. 154 program branches ............................................................... 9 program memory paging ....................................................................... 41 program memory maps PIC16C70 .................................................................. 21 pic16c71 .................................................................. 21 pic16c71a ................................................................ 21 pic16c72 .................................................................. 22 pic16c73 .................................................................. 22 pic16c73a ................................................................ 22 pic16c74 .................................................................. 22 pic16c74a ................................................................ 22 program verification ........................................................ 139 ps0 bit ............................................................................... 31 ps1 bit ............................................................................... 31 ps2 bit ............................................................................... 31 psa bit ............................................................................... 31 pspie bit ..................................................................... 35, 54 pspif bit ...................................................................... 37, 54 pspmode bit ........................................................ 49, 51, 54 push ................................................................................. 41 pwrte bit ....................................................................... 122 r r/w bit ............................................................. 84, 88, 89, 90 r/w bit ............................................................................... 77 rbie bit .............................................................................. 32 rbif bit ................................................................ 32, 45, 136 rbpu bit ............................................................................ 31 rc oscillator ............................................................ 125, 128 rcie bit ............................................................................. 35 rcif bit .............................................................................. 37 rcsta register ................................................................ 94 rcv_mode ...................................................................... 92
1995 microchip technology inc. ds30390b-page 297 pic16c7x rd pin ................................................................................ 54 read-modify-write ............................................................. 53 register file ....................................................................... 22 registers initialization conditions ............................................ 129 maps PIC16C70 .......................................................... 23 pic16c71 .......................................................... 23 pic16c71a ........................................................ 23 pic16c72 .......................................................... 24 pic16c73 .......................................................... 24 pic16c73a ........................................................ 24 pic16c74 .......................................................... 24 pic16c74a ........................................................ 24 reset conditions ...................................................... 129 summary .............................................................. 25?8 reset ........................................................................ 121, 126 reset conditions for special registers ........................... 129 retfie instruction ........................................................... 149 retlw instruction ........................................................... 149 return instruction ........................................................ 150 rlf instruction ................................................................. 150 rp0 bit ......................................................................... 22, 30 rp1 bit ............................................................................... 30 rrf instruction ................................................................ 150 rx9 bit ............................................................................... 94 rx9d bit ............................................................................. 94 s s bit .................................................................................... 77 scl .............................................................................. 88, 91 sda .............................................................................. 90, 91 serial communication interface (sci) module, see usart serial peripheral interface (spi) ........................................ 77 services one-time-programmable (otp) ................................. 7 quick-turnaround-production (qtp) ........................... 7 serialized quick-turnaround production (sqtp) ........ 7 sleep ..................................................................... 121, 126 sleep instruction ............................................................ 150 software simulator (mpsim) ........................................... 157 spbrg register ................................................................ 29 special event trigger ....................................................... 118 special features of the cpu ........................................... 121 special function registers PIC16C70 .................................................................. 25 pic16c71 .................................................................. 25 pic16c71a ................................................................ 25 pic16c72 .................................................................. 26 pic16c73 .................................................................. 28 pic16c73a ................................................................ 28 pic16c74 .................................................................. 28 pic16c74a ................................................................ 28 special function registers, section .................................. 25 spen bit ............................................................................ 94 spi, see synchronous serial port sren bit ............................................................................ 94 ss bit ................................................................................. 81 sspadd register .................................................. 27, 29, 88 sspbuf register ........................................................ 28, 88 sspcon register ................................................. 28, 78, 89 sspen bit .......................................................................... 78 sspie bit ............................................................................ 34 sspif bit .......................................................... 36, 37, 88, 89 sspm0 bit .......................................................................... 78 sspm1 bit .......................................................................... 78 sspm2 bit ...........................................................................78 sspm3 bit ...........................................................................78 sspov bit ....................................................................78, 88 sspsr register .................................................................88 sspstat register ...........................................27, 29, 77, 89 stack ...................................................................................41 overflows ....................................................................41 underflow ...................................................................41 status register ...............................................................30 sublw instruction ...........................................................151 subwf instruction ...........................................................151 swapf instruction ...........................................................152 sync bit .............................................................................93 synchronous serial port i 2 c addressing .........................................................88 addressing i 2 c devices .....................................84 arbitration ...........................................................86 block diagram ....................................................87 clock synchronization ........................................86 combined format ...............................................85 i 2 c operation .....................................................87 i 2 c overview ......................................................83 initiating and terminating data transfer ............83 master-receiver sequence ................................85 master-transmitter sequence ............................85 multi-master ........................................................86 multi-master mode ..............................................91 reception ...........................................................89 slave mode ........................................................88 start ..........................................................83, 90 start (s) ..........................................................91 stop ............................................................83, 84 stop (p) ............................................................91 transfer acknowledge ........................................84 transmission ......................................................90 spi block diagram ....................................................79 block diagram of master/slave connection .......80 master mode ......................................................80 serial clock ........................................................79 serial data in ......................................................79 serial data out ...................................................79 slave select .......................................................79 spi clock ............................................................80 spi mode ............................................................79 sspbuf register ...............................................80 sspsr register .................................................80 synchronous serial port module ........................................77 t t0cs bit ..............................................................................31 t0ie bit ...............................................................................32 t0if bit ...............................................................................32 t1ckps0 bit .......................................................................65 t1ckps1 bit .......................................................................65 t1con register .................................................................65 t1oscen bit ......................................................................65 t1sync bit .........................................................................65 t2ckps0 bit .......................................................................70 t2ckps1 bit .......................................................................70 t2con register .................................................................70 t ad ...................................................................................115 timer modules, overview ...................................................57 timer0 rtcc ........................................................................129
pic16c7x ds30390b-page 298 1995 microchip technology inc. timers timer0 block diagram .................................................... 59 external clock .................................................... 61 external clock timing ........................................ 61 increment delay ................................................. 61 interrupt .............................................................. 59 interrupt timing .................................................. 60 overview ............................................................ 57 prescaler ............................................................ 62 prescaler block diagram ................................... 62 section ............................................................... 59 switching prescaler assignment ........................ 63 synchronization ................................................. 61 t0cki ................................................................. 61 t0if .................................................................. 136 timing ................................................................ 59 tmr0 interrupt ................................................. 136 timer1 asynchronous counter mode ............................ 67 block diagram .................................................... 66 capacitor selection ............................................ 67 external clock input ........................................... 66 external clock input timing ............................... 67 operation in timer mode ................................... 66 oscillator ............................................................ 67 overview ............................................................ 57 prescaler ...................................................... 66, 68 resetting of timer1 registers ........................... 68 resetting timer1 using a ccp trigger output .. 68 synchronized counter mode ............................. 66 t1con ............................................................... 65 tmr1h ............................................................... 67 tmr1l ............................................................... 67 timer2 block diagram .................................................... 69 module ............................................................... 69 overview ............................................................ 57 postscaler .......................................................... 69 prescaler ............................................................ 69 t2con ............................................................... 70 timing diagrams a/d conversion ........................ 172, 187, 215, 239, 263 brown-out reset .............................. 127, 168, 206, 253 capture/compare/pwm ........................... 208, 231, 255 clkout and i/o ...................... 167, 182, 205, 228, 252 external clock timing .............. 166, 181, 204, 226, 250 i 2 c bus data ............................................ 211, 235, 259 i 2 c bus start/stop bits ............................. 210, 234, 258 i 2 c clock synchronization ......................................... 86 i 2 c data transfer wait state ..................................... 84 i 2 c multi-master arbitration ........................................ 86 i 2 c reception ............................................................. 89 i 2 c transmission ....................................................... 90 parallel slave port ........................................... 232, 256 power-up timer ....................... 168, 183, 206, 229, 253 reset ........................................ 168, 183, 206, 229, 253 spi mode ................................................. 209, 233, 257 spi mode timing (no ss control) ............................. 81 spi mode timing (ss control) ................................... 81 start-up timer .......................... 168, 183, 206, 229, 253 time-out sequence .................................................. 131 timer0 ................................ 59, 169, 184, 207, 230, 254 timer0 interrupt timing .............................................. 60 timer0 with external clock ........................................ 61 timer1 ...................................................... 207, 230, 254 usart asynchronous master transmission .......... 100 usart asynchronous reception ........................... 101 usart rx pin sampling .......................................... 98 usart synchronous receive ........................ 236, 260 usart synchronous reception ............................. 106 usart synchronous transmission ........ 104, 236, 260 wake-up from sleep via interrupt ............................ 138 watchdog timer ...................... 168, 183, 206, 229, 253 tmr0 register ................................................................... 28 tmr1cs bit ....................................................................... 65 tmr1h register .......................................................... 26, 28 tmr1ie bit ......................................................................... 34 tmr1if bit ................................................................... 36, 37 tmr1l register ........................................................... 26, 28 tmr1on bit ....................................................................... 65 tmr2 register ............................................................. 26, 28 tmr2ie bit ......................................................................... 34 tmr2if bit ................................................................... 36, 37 tmr2on bit ....................................................................... 70 to bit ................................................................................. 30 toutps0 bit ..................................................................... 70 toutps1 bit ..................................................................... 70 toutps2 bit ..................................................................... 70 toutps3 bit ..................................................................... 70 tris instruction ............................................................... 152 trisa register ................................................ 25, 27, 29, 43 trisb register ................................................ 25, 27, 29, 45 trisc register ...................................................... 27, 29, 47 trisd register ...................................................... 25, 29, 49 trise register ............................................................ 29, 51 trmt bit ............................................................................ 93 two? complement .............................................................. 9 tx9 bit ............................................................................... 93 tx9d bit ............................................................................. 93 txen bit ............................................................................ 93 txie bit .............................................................................. 35 txif bit .............................................................................. 37 txsta register ................................................................. 93 u ua bit ................................................................................. 77 universal synchronous asynchronous receiver transmitter (usart) ............................................................................ 93 usart asynchronous mode .................................................. 99 asynchronous receiver ........................................... 101 asynchronous reception ......................................... 102 asynchronous transmission ................................... 100 asynchronous transmitter ......................................... 99 baud rate generator (brg) ..................................... 95 receive block diagram ........................................... 101 sampling .................................................................... 98 synchronous master mode ...................................... 103 synchronous master reception .............................. 105 synchronous master transmission ......................... 103 synchronous slave mode ........................................ 107 synchronous slave reception ................................ 107 synchronous slave transmit ................................... 107 transmit block diagram ............................................ 99 uv erasable devices ........................................................... 7 w w register alu .............................................................................. 9 wake-up from sleep ...................................................... 138 watchdog timer (wdt) ........................... 121, 126, 129, 137 wcol bit ........................................................................... 78
1995 microchip technology inc. ds30390b-page 299 pic16c7x wdt ................................................................................. 129 block diagram .......................................................... 137 period ....................................................................... 137 programming considerations .................................. 137 timeout .................................................................... 129 wdte bit .......................................................................... 122 word ................................................................................ 122 wr pin ............................................................................... 54 x xmit_mode ...................................................................... 92 xorlw instruction .......................................................... 152 xorwf instruction .......................................................... 152 z z bit .................................................................................... 30 zero bit ................................................................................. 9 list of examples example 3-1: instruction pipeline flow........................... 20 example 4-1: call of a subroutine in page 1 from page 0 ...................................................... 42 example 4-2: indirect addressing................................... 42 example 5-1: initializing porta .................................... 43 example 5-2: initializing portb ................................... 45 example 5-3: initializing portc .................................... 47 example 5-4: read-modify-write instructions on an i/o port ..................................................... 53 example 7-1: changing prescaler (timer0 ? wdt)........ 63 example 7-2: changing prescaler (wdt ? timer0)........ 63 example 8-1: reading a 16-bit free-running timer ...... 67 example 10-1: changing between capture prescalers ... 73 example 11-1: loading the sspbuf (sspsr) register .................................................... 79 example 12-1: calculating baud rate error..................... 95 equation 13-1: a/d minimum charging time ................. 114 example 13-1: calculating the minimum required sample time .......................................... 114 example 13-2: doing an a/d conversion (PIC16C70/71/71a) ................................ 116 example 13-3: doing an a/d conversion (pic16c72/73/73a/74/74a).................... 116 example 13-4: 4-bit vs. 8-bit conversion times ............. 117 example 14-1: saving status and w registers in ram (PIC16C70/71/71a) ................................ 136 example 14-2: saving status and w registers in ram (pic16c72/73/73a/74/74a).................... 136 list of figures figure 3-1: PIC16C70/71/71a block diagram............. 10 figure 3-2: pic16c72 block diagram ......................... 11 figure 3-3: pic16c73/73a block diagram.................. 12 figure 3-4: pic16c74/74a block diagram.................. 13 figure 3-5: clock/instruction cycle.............................. 20 figure 4-1: PIC16C70 program memory map and stack ......................................................... 21 figure 4-2: pic16c71/71a program memory map and stack .................................................. 21 figure 4-3: pic16c72 program memory map and stack ......................................................... 22 figure 4-4: pic16c73/73a/74/74a program memory map and stack .......................................... 22 figure 4-5: PIC16C70/71 register file map ............... 23 figure 4-6: pic16c71a register file map .................. 23 figure 4-7: pic16c72 register file map .................... 24 figure 4-8: pic16c73/73a/74/74a register file map ........................................................... 24 figure 4-9: status register (address 03h, 83h)...........30 figure 4-10: option register (address 81h) ...............31 figure 4-11: intcon register for PIC16C70/71/71a (address 0bh, 8bh) ...................................32 figure 4-12: intcon register for pic16c72/73/ 73a/74/74a (address 0bh, 8bh)................33 figure 4-13: pie1 register pic16c72 (address 8ch)...34 figure 4-14: pie1 register pic16c73/73a/74/74a (address 8ch)............................................35 figure 4-15: pir1 register pic16c72 (address 0ch)...36 figure 4-16: pir1 register pic16c73/73a/74/74a (address 0ch)............................................37 figure 4-17: pie2 register (address 8dh) ....................38 figure 4-18: pir2 register (address 0dh) ....................39 figure 4-19: pcon register (address 8eh) ..................40 figure 4-20: loading of pc in different situations.........41 figure 4-21: direct/indirect addressing..........................42 figure 5-1: block diagram of ra3:ra0 and ra5 pins 43 figure 5-2: block diagram of ra4/t0cki pin ..............44 figure 5-3: block diagram of rb3:rb0 pins ...............45 figure 5-4: block diagram of rb7:rb4 pins ...............45 figure 5-5: portc block diagram (peripheral output override)....................................................47 figure 5-6: portd block diagram (in i/o port mode) 49 figure 5-7: trise register (address 89h) ..................51 figure 5-8: porte block diagram (in i/o port mode) 52 figure 5-9: successive i/o operation ..........................53 figure 5-10: portd and porte block diagram (parallel slave port)...................................54 figure 7-1: timer0 block diagram ...............................59 figure 7-2: timer0 timing: internal clock/no prescale.....................................................59 figure 7-3: timer0 timing: internal clock/ prescale 1:2...............................................60 figure 7-4: timer0 interrupt timing .............................60 figure 7-5: timer0 timing with external clock ............61 figure 7-6: block diagram of the timer0/wdt prescaler....................................................62 figure 8-1: t1con: timer1 control register (address 10h) ............................................65 figure 8-2: timer1 block diagram ...............................66 figure 9-1: timer2 block diagram ...............................69 figure 9-2: t2con: timer2 control register (address 12h) ............................................70 figure 10-1: ccp1con register (address 17h)/ ccp2con register (address 1dh)...........72 figure 10-2: capture mode operation block diagram...73 figure 10-3: compare mode operation block diagram.73 figure 10-4: simplified pwm block diagram .................74 figure 11-1: sspstat: sync serial port status register (address 94h) ............................................77 figure 11-2: sspcon: sync serial port control register (address 14h) ............................................78 figure 11-3: ssp block diagram (spi mode) ................79 figure 11-4: spi master/slave connection....................80 figure 11-5: spi mode timing (master mode or slave mode w/o ss control)................................81 figure 11-6: spi mode timing (slave mode with ss control) ................................................81 figure 11-7: start and stop conditions..........................83 figure 11-8: 7-bit address format .................................84 figure 11-9: i 2 c 10-bit address format .........................84 figure 11-10: slave-receiver acknowledge ....................84 figure 11-11: data transfer wait state ...........................84 figure 11-12: master-transmitter sequence ....................85 figure 11-13: master-receiver sequence.........................85
pic16c7x ds30390b-page 300 1995 microchip technology inc. figure 11-14: combined format ..................................... 85 figure 11-15: multi-master arbitration (two masters) ..... 86 figure 11-16: clock synchronization............................... 86 figure 11-17: ssp block diagram (i 2 c mode) ................ 87 figure 11-18: i 2 c waveforms for reception (7-bit address)........................................... 89 figure 11-19: i 2 c waveforms for transmission (7-bit address)........................................... 90 figure 11-20: operation of the i2c module in idle_mode, rcv_mode or xmit_mode ................... 92 figure 12-1: txsta: transmit status and control register (address 98h) ............................. 93 figure 12-2: rcsta: receive status and control register (address 18h)............................. 94 figure 12-3: rx pin sampling scheme (brgh = 0) ..... 98 figure 12-4: rx pin sampling scheme (brgh = 1) ..... 98 figure 12-5: rx pin sampling scheme (brgh = 1) ..... 98 figure 12-6: usart transmit block diagram............... 99 figure 12-7: asynchronous master transmission ....... 100 figure 12-8: asynchronous master transmission (back to back)......................................... 100 figure 12-9: usart receive block diagram.............. 101 figure 12-10: asynchronous reception ........................ 101 figure 12-11: synchronous transmission..................... 104 figure 12-12: synchronous transmission (through txen)...................................... 104 figure 12-13: synchronous reception (master mode, sren) ..................................................... 106 figure 13-1: adcon0 register, PIC16C70/71/71a (address 08h).......................................... 109 figure 13-2: adcon0 register, pic16c72/73/73a/74/ 74a (address 1fh) .................................. 110 figure 13-3: adcon1 register for PIC16C70/71/71a (address 88h).......................................... 110 figure 13-4: adcon1 register, pic16c72/73/73a/74/ 74a (address 9fh) .................................. 111 figure 13-5: a/d block diagram, PIC16C70/71/71a... 112 figure 13-6: a/d block diagram, pic16c72/73/73a/74/ 74a.......................................................... 113 figure 13-7: analog input model ................................. 114 figure 13-8: a/d transfer function ............................. 119 figure 13-9: flowchart of a/d operation..................... 119 figure 14-1: configuration word for pic16c71 .......... 121 figure 14-2: configuration word for PIC16C70/71a ... 122 figure 14-3: configuration word for pic16c73/74 ..... 122 figure 14-4: configuration word for pic16c72/73a/ 74a.......................................................... 123 figure 14-5: crystal/ceramic resonator operation (hs, xt or lp osc configuration) ......... 123 figure 14-6: external clock input operation (hs, xt or lp osc configuration) ......... 123 figure 14-7: external parallel resonant crystal oscillator circuit ...................................................... 125 figure 14-8: external series resonant crystal oscillator circuit ...................................................... 125 figure 14-9: rc oscillator mode ................................. 125 figure 14-10: simplified block diagram of on-chip reset circuit ...................................................... 126 figure 14-11: brown-out situations ............................... 127 figure 14-12: time-out sequence on power-up (mclr not tied to v dd ): case 1............. 131 figure 14-13: time-out sequence on power-up (mclr not tied to v dd ): case 2 ........... 131 figure 14-14: time-out sequence on power-up (mclr tied to v dd ) ................................ 131 figure 14-15: external power-on reset circuit (for slow v dd power-up) ........................................ 132 figure 14-16: external brown-out protection circuit 1.. 132 figure 14-17: external brown-out protection circuit 2.. 132 figure 14-18: interrupt logic for PIC16C70/71/71a...... 134 figure 14-19: interrupt logic for pic16c72 .................. 134 figure 14-20: interrupt logic for pic16c73/73a........... 134 figure 14-21: interrupt logic for pic16c74/74a........... 135 figure 14-22: int pin interrupt timing.......................... 135 figure 14-23: watchdog timer block diagram ............. 137 figure 14-24: summary of watchdog timer registers. 137 figure 14-25: wake-up from sleep through interrupt .. 138 figure 14-26: typical in-circuit serial programming connection.............................................. 139 figure 15-1: general format for instructions .............. 141 figure 16-1: picmaster system configuration ....... 153 figure 17-1: load conditions...................................... 165 figure 17-2: external clock timing............................. 166 figure 17-3: clkout and i/o timing......................... 167 figure 17-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing ......... 168 figure 17-5: brown-out reset timing ......................... 168 figure 17-6: timer0 clock timings ............................. 169 figure 17-7: a/d conversion timing........................... 172 figure 19-1: load conditions...................................... 180 figure 19-2: external clock timing............................. 181 figure 19-3: clkout and i/o timing......................... 182 figure 19-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing ......... 183 figure 19-5: timer0 clock timings ............................. 184 figure 19-6: a/d conversion timing........................... 187 figure 20-1: typical rc oscillator frequency vs. temperature ........................................... 189 figure 20-2: typical rc oscillator frequency vs. v dd ......................................................... 189 figure 20-3: typical rc oscillator frequency vs. v dd ......................................................... 189 figure 20-4: typical rc oscillator frequency vs. v dd 190 figure 20-5: typical ipd vs. v dd watchdog timer disabled 25 c......................................... 190 figure 20-6: typical ipd vs. v dd watchdog timer enabled 25 c.......................................... 190 figure 20-7: maximum ipd vs. v dd watchdog disabled.................................................. 191 figure 20-8: maximum ipd vs. v dd watchdog enabled................................................... 191 figure 20-9: vth (input threshold voltage) of i/o pins vs. v dd ......................................................... 191 figure 20-10: vih, vil of mclr , t0cki and osc1 (in rc mode) vs. v dd ........................................ 192 figure 20-11: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd ........ 192 figure 20-12: typical i dd vs. freq (ext clock, 25 c).... 193 figure 20-13: maximum, i dd vs. freq (ext clock, -40 to +85 c) .................................................... 193 figure 20-14: maximum idd vs. freq with a/d off (ext clock, -55 to +125 c) .................... 194 figure 20-15: wdt timer time-out period vs. v dd ...... 194 figure 20-16: transconductance (gm) of hs oscillator vs. v dd ......................................................... 194 figure 20-17: transconductance (gm) of lp oscillator vs. v dd ......................................................... 195 figure 20-18: transconductance (gm) of xt oscillator vs. v dd ......................................................... 195 figure 20-19: ioh vs. voh, v dd = 3v .......................... 195 figure 20-20: ioh vs. voh, v dd = 5v .......................... 195 figure 20-21: iol vs. vol, v dd = 3v ........................... 196 figure 20-22: iol vs. vol, v dd = 5v ........................... 196
1995 microchip technology inc. ds30390b-page 301 pic16c7x figure 21-1: load conditions ...................................... 203 figure 21-2: external clock timing ............................. 204 figure 21-3: clkout and i/o timing ......................... 205 figure 21-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing.......... 206 figure 21-5: brown-out reset timing.......................... 206 figure 21-6: timer0 and timer1 clock timings .......... 207 figure 21-7: capture/compare/pwm timings (ccp1) .................................................... 208 figure 21-8: spi mode timing..................................... 209 figure 21-9: i 2 c bus start/stop bits timing ................ 210 figure 21-10: i 2 c bus data timing ............................... 211 figure 21-11: a/d conversion timing ........................... 215 figure 23-1: load conditions ...................................... 225 figure 23-2: external clock timing ............................. 226 figure 23-3: clkout and i/o timing ......................... 228 figure 23-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing.......... 229 figure 23-5: timer0 and timer1 clock timings .......... 230 figure 23-6: capture/compare/pwm timings (ccp1 and ccp2) ..................................................... 231 figure 23-7: parallel slave port timing for the pic16c74 only......................................................... 232 figure 23-8: spi mode timing..................................... 233 figure 23-9: i 2 c bus start/stop bits timing ................ 234 figure 23-10: i 2 c bus data timing ............................... 235 figure 23-11: usart module: synchronous transmission (master/slave) timing ............................. 236 figure 23-12: usart module: synchronous receive (master/slave) timing ............................. 236 figure 23-13: a/d conversion timing ........................... 239 figure 25-1: load conditions ...................................... 249 figure 25-2: external clock timing ............................. 250 figure 25-3: clkout and i/o timing ......................... 252 figure 25-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing.......... 253 figure 25-5: brown-out reset timing.......................... 253 figure 25-6: timer0 and timer1 clock timings .......... 254 figure 25-7: capture/compare/pwm timings (ccp1 and ccp2) ..................................................... 255 figure 25-8: parallel slave port timing for the pic16c74a only......................................................... 256 figure 25-9: spi mode timing..................................... 257 figure 25-10: i 2 c bus start/stop bits timing ................ 258 figure 25-11: i 2 c bus data timing ............................... 259 figure 25-12: usart module: synchronous transmission (master/slave) timing ............................. 260 figure 25-13: usart module: synchronous receive (master/slave) timing ............................. 260 figure 25-14: a/d conversion timing ........................... 263 list of tables table 1-1: pic16c7x family of devices...................... 6 table 3-1: PIC16C70/71a pinout description ............ 14 table 3-2: pic16c71 pinout description ................... 15 table 3-3: pic16c72 pinout description ................... 16 table 3-4: pic16c73/73a pinout description ............ 17 table 3-5: pic16c74/74a pinout description ............ 18 table 4-1: PIC16C70/71/71a special function register summary................................................... 25 table 4-2: pic16c72 special function register summary................................................... 26 table 4-3: pic16c73/73a/74/74a special function register summary .................................... 28 table 5-1: porta functions ..................................... 44 table 5-2: summary of registers associated with porta ......................................................44 table 5-3: portb functions......................................46 table 5-4: summary of registers associated with portb ......................................................46 table 5-5: portc functions......................................48 table 5-6: summary of registers associated with portc ......................................................48 table 5-7: portd functions......................................49 table 5-8: summary of registers associated with portd ......................................................50 table 5-9: porte functions......................................52 table 5-10: summary of registers associated with porte ......................................................52 table 5-11: registers associated with parallel slave port ............................................................55 table 7-1: registers associated with timer0, PIC16C70/71/71a......................................63 table 7-2: registers associated with timer0, pic16c72/73/73a/74/74a .........................63 table 8-1: capacitor selection for the timer1 oscillator....................................................67 table 8-2: registers associated with timer1 as a timer/counter............................................68 table 9-1: registers associated with timer2 as a timer/counter............................................70 table 10-1: ccp mode - timer resource ....................71 table 10-2: interaction of two ccp modules ...............71 table 10-3: pwm frequency vs. resolution at 20 mhz ......................................................74 table 10-4: example pwm frequencies and resolutions at 20 mhz ..................................................74 table 10-5: registers associated with capture and timer1........................................................75 table 10-6: registers associated with compare and timer1........................................................75 table 10-7: registers associated with pwm and timer2........................................................76 table 11-1: registers associated with spi operation ..82 table 11-2: i 2 c bus terminology..................................83 table 11-3: data transfer received byte actions........88 table 11-4: registers associated with i 2 c operation...91 table 12-1: baud rate formula....................................95 table 12-2: registers associated with baud rate generator...................................................95 table 12-3: baud rates for synchronous mode...........96 table 12-4: baud rates for asynchronous mode (brgh = 0)................................................96 table 12-5: baud rates for asynchronous mode (brgh = 1)................................................97 table 12-6: registers associated with asynchronous transmission ...........................................100 table 12-7: registers associated with asynchronous reception.................................................102 table 12-8: registers associated with synchronous master transmission ...............................104 table 12-9: registers associated with synchronous master reception.....................................105 table 12-10: registers associated with synchronous slave transmission .................................108 table 12-11: registers associated with synchronous slave reception.......................................108 table 13-1: t ad vs. device operating frequencies, pic16c71 ................................................115 table 13-2: t ad vs. device operating frequencies, PIC16C70/71a/72/73/73a/74/74a ...........115
pic16c7x ds30390b-page 302 1995 microchip technology inc. table 13-3: summary of a/d registers, PIC16C70/71/ 71a.......................................................... 120 table 13-4: summary of a/d registers, pic16c72 ... 120 table 13-5: summary of a/d registers, pic16c73/73a/ 74/74a..................................................... 120 table 14-1: ceramic resonators pic16c71.............. 124 table 14-2: capacitor selection for crystal oscillator for pic16c71................................................ 124 table 14-3: ceramic resonators PIC16C70/71a/72/73/ 73a/74/74a ............................................. 124 table 14-4: capacitor selection for crystal oscillator for PIC16C70/71a/72/73/73a/74/74a .......... 124 table 14-5: time-out in various situations, pic16c71/ 73/74 ....................................................... 128 table 14-6: time-out in various situations, PIC16C70/ 71a/72/73a/74a ...................................... 128 table 14-7: status bits and their significance, pic16c71/73/74...................................... 128 table 14-8: status bits and their significance, PIC16C70/71a/72/73a/74a .................... 128 table 14-9: reset condition for special registers .... 129 table 14-10: initialization conditions for all registers . 129 table 15-1: opcode field descriptions ...................... 141 table 15-2: pic16cxx instruction set....................... 142 table 16-1: picmaster probe specification ........... 154 table 16-2: development system packages ............. 157 table 17-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ............ 160 table 17-2: clock timing requirements .................... 166 table 17-3: clkout and i/o timing requirements.. 167 table 17-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements .... 168 table 17-5: timer0 clock requirements.................... 169 table 17-6: a/d converter characteristics: PIC16C70-04 (commercial, industrial, automotive) pic16c71a-04 (commercial, industrial, automotive) PIC16C70-10 (commercial, industrial, automotive) pic16c71a-10 (commercial, industrial, automotive) PIC16C70-20 (commercial, industrial, automotive) pic16c71a-20 (commercial, industrial, automotive) ............................................. 170 table 17-7: a/d converter characteristics: pic16lc70-04 (commercial, industrial, automotive) pic16lc71a-04 (commercial, industrial, automotive) ............................................. 171 table 17-8: a/d conversion requirements................ 172 table 19-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ............ 175 table 19-2: external clock timing requirements...... 181 table 19-3: clkout and i/o timing requirements.. 182 table 19-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements.......................................... 183 table 19-5: timer0 clock requirements.................... 184 table 19-6: a/d converter characteristics: pic16c71-04 (commercial, industrial) pic16c71-20 (commercial, industrial) ... 185 table 19-7: a/d converter characteristics: pic16lc71-04 (commercial, industrial). 186 table 19-8: a/d conversion requirements ............... 187 table 20-1: rc oscillator frequencies...................... 190 table 20-2: input capacitance* ................................. 196 table 21-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices)........ 198 table 21-2: clock timing requirements.................... 204 table 21-3: clkout and i/o timing requirements . 205 table 21-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements ......................................... 206 table 21-5: timer0 and timer1 clock requirements 207 table 21-6: capture/compare/pwm requirements (ccp1).................................................... 208 table 21-7: spi mode requirements......................... 209 table 21-8: i 2 c bus start/stop bits requirements .... 210 table 21-9: i 2 c bus data requirements ................... 211 table 21-10: serial port synchronous transmission requirements ......................................... 212 table 21-11: serial port synchronous receive requirements ......................................... 212 table 21-12: a/d converter characteristics: pic16c72-04 (commercial, industrial, automotive) pic16c72-10 (commercial, industrial, automotive) pic16c72-20 (commercial, industrial, automotive)............................................. 213 table 21-13: a/d converter characteristics: pic16lc72-04 (commercial, industrial, automotive)............................................. 214 table 21-14: a/d conversion requirements ............... 215 table 23-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices)........ 220 table 23-2: clock timing requirements.................... 226 table 23-3: clkout and i/o timing requirements . 228 table 23-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements ......................................... 229 table 23-5: timer0 and timer1 clock requirements 230 table 23-6: capture/compare/pwm requirements (ccp1 and ccp2) .................................. 231 table 23-7: parallel slave port requirements for the pic16c74 only....................................... 232 table 23-8: spi mode requirements......................... 233 table 23-9: i 2 c bus start/stop bits requirements .... 234 table 23-10: i 2 c bus data requirements ................... 235 table 23-11: serial port synchronous transmission requirements ......................................... 236 table 23-12: serial port synchronous receive requirements ......................................... 236 table 23-13: a/d converter characteristics: pic16c73-04 (commercial, industrial) pic16c74-04 (commercial, industrial) pic16c73-10 (commercial, industrial) pic16c74-10 (commercial, industrial) pic16c73-20 (commercial, industrial) pic16c74-20 (commercial, industrial)... 237 table 23-14: a/d converter characteristics: pic16lc73-04 (commercial, industrial) pic16lc74-04 (commercial, industrial). 238 table 23-15: a/d conversion requirements ............... 239
1995 microchip technology inc. ds30390b-page 303 pic16c7x table 25-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ........ 244 table 25-2: clock timing requirements .................... 250 table 25-3: clkout and i/o timing requirements.. 252 table 25-4: reset, watchdog timer, oscillator start-up timer and power-up timer requirements.......................................... 253 table 25-5: timer0 and timer1 clock requirements 254 table 25-6: capture/compare/pwm requirements (ccp1 and ccp2)................................... 255 table 25-7: parallel slave port requirements for the pic16c74a only..................................... 256 table 25-8: spi mode requirements ......................... 257 table 25-9: i 2 c bus start/stop bits requirements .... 258 table 25-10: i 2 c bus data requirements.................... 259 table 25-11: serial port synchronous transmission requirements.......................................... 260 table 25-12: serial port synchronous receive requirements.......................................... 260 table 25-13: a/d converter characteristics: pic16c73a-04 (commercial, industrial, automotive) pic16c74a-04 (commercial, industrial, automotive) pic16c73a-10 (commercial, industrial, automotive) pic16c74a-10 (commercial, industrial, automotive) pic16c73a-20 (commercial, industrial, automotive) pic16c74a-20 (commercial, industrial, automotive) ............................................. 261 table 25-14: a/d converter characteristics: pic16lc73a-04 (commercial, industrial, automotive) pic16lc74a-04 (commercial, industrial, automotive)..............................................262 table 25-15: a/d conversion requirements ................263 table e-1: pic16c5x family of devices ..................285 table e-2: pic16c62x family of devices ................286 table e-3: pic16c6x family of devices ..................287 table e-4: pic16c7x family of devices ..................288 table e-5: pic16c8x family of devices ..................289 table e-6: pic17cxx family of devices ..................290 table e-7: pin compatible devices...........................291
pic16c7x ds30390b-page 304 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30390b-page 305 pic16c7x connecting to microchip bbs connect worldwide to the microchip bbs using the compuserve communications network. in most cases a local call is your only expense. the microchip bbs connection does not use compuserve member- ship services, therefore you do not need compuserve membership to join microchip's bbs . there is no charge for connecting to the bbs, except for a toll charge to the compuserve access number, where applicable. you do not need to be a compuserve member to take advantage of this con- nection (you never actually log in to compuserve). the procedure to connect will vary slightly from country to country. please check with your local compuserve agent for details if you have a problem. compuserve service allows multiple users at baud rates up to 14400 bps. the following connect procedure applies in most loca- tions: 1. set your modem to 8 bit, no parity, and one stop (8n1). this is not the normal compuserve set- ting which is 7e1. 2. dial your local compuserve access number. 3. depress and a garbage string will appear because compuserve is expecting a 7e1 setting. 4. type +, depress and host name: will appear. 5. type mchipbbs, depress < enter ? > and you will be connected to the microchip bbs. in the united states, to ?d compuserve's phone num- ber closest to you, set your modem to 7e1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. after the system responds with host name: , type network, depress < enter ? > and follow compuserve's directions. for voice information (or calling from overseas), you may call (614) 457-1550 for your local compuserve number. trademarks: the microchip logo, name and pic are registered trademarks of microchip technology incorporated in the u.s.a. picmaster, mplab, picstart, pro mate and fuzzylab are trademarks, and sqtp is a ser- vice mark of microchip technology incorporated. fuzzytech is a registered trademark of inform software corporation. i 2 c is a trademark of philips corporation. ibm, ibm pc-at are registered trademarks of international business machines corp. pentium is a trademark of intel corporation. ms-dos and microsoft windows are registered trademarks of microsoft corporation. windows is a trademark of microsoft corporation. compuserve is a registered trademark of compuserve incorporated. all other trademarks mentioned herein are the property of their respective companies. this document was created with framemake r404
pic16c7x ds30390b-page 306 1995 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you ?d the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefullness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30390b pic16c7x
pic16c7x pic16c7x pr oduct identi cation system to order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales of?e. 1995 microchip technology inc. ds30390b-page 307 * jw devices are uv erasable and can be programmed to any device con?uration. jw devices meet the electrical requirement of each oscillator type (including lc devices). part no. -xx x /xx xxx pattern: qtp, sqtp, rom code or special requirements package: jw = windowed cerdip pq = mqfp (metric pqfp) tq = tqfp (thin quad flatpack) so = soic sp = skinny plastic carrier sj = skinny cerdip p = pdip l = plcc temperature range: -=0 c to +70 c (t for tape/reel) i = -40 c to +85 c (s for tape/reel) e = -40 c to +125 c frequency range: 04 = 200 khz (pic16c7x-04) 04 = 4 mhz 10 = 10 mhz 16 = 16 mhz 20 = 20 mhz device pic16c7x : v dd range 4.0v to 6.0v pic16c7xt : v dd range 4.0v to 6.0v (tape/reel) pic16lc7x : v dd range 3.0v to 6.0v pic16lc7xt : v dd range 3.0v to 6.0v (tape/reel) examples a) pic16c71 - 04/p 301 commercial temp., pdip package, 4 mhz, normal v dd limits, qtp pattern #301 b) pic16lc73 - 041/so industrial temp., soic package, 4 mhz, extended v dd limits c) pic16c74a - 10e/p automotive temp., pdip package, 10 mhz, normal v dd limits sales and suppor t products supported by a preliminary data sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: your local microchip sales of?e (see below) the microchip corporate literature center u.s. fax: (602) 786-7277 the microchips bulletin board, via your local compuserve number (compuserve membership not required). please specify which device, revision of silicon and data sheet (include literature #) you are using. for latest version information and upgrade kits for microchip development tools, please call 1-800-755-2345 or 1-602-786-7302. 1. 2. 3. this document was created with framemake r404
printed in the usa, 12/5/95 1995, microchip technology inc. ds30390b-page 308 1995 microchip technology inc. w orldwide s ales & s ervice americas (continued) san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408 436-7950 fax: 408 436-7955 asia/pacific hong kong microchip technology unit no. 3002-3004, tower 1 metroplaza 223 hing fong road kwai fong, n.t. hong kong tel: 852 2 401 1200 fax: 852 2 401 3431 korea microchip technology 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku, seoul, korea tel: 82 2 554 7200 fax: 82 2 558 5934 singapore microchip technology 200 middle road #10-03 prime centre singapore 188980 tel: 65 334 8870 fax: 65 334 8850 taiwan microchip technology 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2 717 7175 fax: 886 2 545 0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44 0 1628 851077 fax: 44 0 1628 850259 france arizona microchip technology sarl 2 rue du buisson aux fraises 91300 massy - france tel: 33 1 69 53 63 20 fax: 33 1 69 30 90 79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 muenchen, germany tel: 49 89 627 144 0 fax: 49 89 627 144 44 italy arizona microchip technology srl centro direzionale colleoni palazzo pegaso ingresso no. 2 via paracelso 23, 20041 agrate brianza (mi) italy tel: 39 039 689 9939 fax: 39 039 689 9883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81 45 471 6166 fax: 81 45 471 6122 americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602 786-7200 fax: 602 786-7277 technical support: 602 786-7627 web: http://www.mchip.com/microchip atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770 640-0034 fax: 770 640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508 480-9990 fax: 508 480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 708 285-0071 fax: 708 285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 214 991-7177 fax: 214 991-8588 dayton microchip technology, inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 513 291-1654 fax: 513 291-9175 los angeles microchip technology inc. 18201 von karman, suite 455 irvine, ca 92715 tel: 714 263-1888 fax: 714 263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516 273-5305 fax: 516 273-5335 information contained in this publication regarding device applications and the like is intended by way of suggestion only. no representation or warranty is given and no liability is assumed by microchip technology inc. with respect to the accuracy or use of such information. use of microchips products as critical components in life support systems is not autho- rized except with express written approval by microchip. the microchip logo and name are registered trademarks of microchip technology inc. all rights reserved. all other trademarks mentioned herein are the property of their respective companies.

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